Extensible vector operation cluster

Abstract

The invention relates to an extensible vector operation cluster, comprising a vector processing array, a vector decoder supporting compression commands, a partial vector register file / accumulator register for storing various data types and a matrix register file supporting rank access, wherein the vector processing array comprises 2-64 isomorphism vector processing units, each vector processing unit comprises an independent partial vector register file / accumulator register and shares the matrix register; and the partial vector register file / accumulator register and the matrix register file provide the data source and destination for command operation. The extensible vector operation cluster has the advantages of simple principle, wide application range and good processing effect, can effectively support various most advanced digital signal processing algorithms and the like.

Description

technical field [0001] The present invention mainly relates to the field of digital signal processors that perform large-scale parallel data processing, and specifically refers to a scalable vector operation cluster, that is, a support vector compression instruction, an internally integrated tightly coupled expansion function unit, and a vector width configurable Scalable cluster of vector operations. Background technique [0002] In the current fast-developing wireless communication, video image, and radar signal processing applications, the algorithm has higher and higher requirements for the performance of the microprocessor. Aiming at the parallelism of a large amount of data in the algorithm program, the current digital signal processor structure adopts different compromise strategies in terms of flexibility, power consumption and performance, and various solutions are proposed. Such as stream processors, array processors, vector processors, etc. Imagine, a representa...

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Problems solved by technology

But it also brings the following problems: tightly coupled reconfigurable functional units, lack of parallelism between the extended functional unit and the basic functional unit, fewer types of extended operations, not suitable for SIMD vector operations, and complex interfaces between the two Inflexible; loosely coupled reconfigurable functional units, low bandwidth for data interaction, high latency

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