Extensible vector operation cluster
A vector operation and vector technology, applied in the field of scalable vector operation clusters, can solve the problems of low data interaction bandwidth, less expansion operation types, complex and inflexible interfaces, etc., to improve application performance, reduce the number of dynamic instructions, and high code. The effect of density
Active Publication Date: 2011-04-13
NAT UNIV OF DEFENSE TECH
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But it also brings the following problems: tightly coupled reconfigurable functional units, lack of parallelism between the extended functional unit and the basic functional unit, fewer types of extended operations, not suitable for SIMD vector operations, and complex interfaces between the two Inflexible; loosely coupled reconfigurable functional units, low bandwidth for data interaction, high latency
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[0025] The present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.
[0026] Such as figure 1 As shown, it is a schematic diagram of the overall framework of the micro-architecture for constructing the scalable vector operation cluster of the present invention. The processor aims to exploit the rich data parallelism found in many signal processors. The whole structure includes scalar processing unit 102 , scalable vector operation cluster of the present invention, address generation unit AGU and vector memory 107 . The scalar or vector instructions dispatched by the instruction dispatch unit are dispatched to corresponding processing units. The scalable vector operation cluster (VPU) of the present invention is a data processing unit at the same level as the scalar unit (SPU). The two receive instructions dispatched by the instruction dispatching part, among which the VPU receives the vector operatio...
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The invention relates to an extensible vector operation cluster, comprising a vector processing array, a vector decoder supporting compression commands, a partial vector register file / accumulator register for storing various data types and a matrix register file supporting rank access, wherein the vector processing array comprises 2-64 isomorphism vector processing units, each vector processing unit comprises an independent partial vector register file / accumulator register and shares the matrix register; and the partial vector register file / accumulator register and the matrix register file provide the data source and destination for command operation. The extensible vector operation cluster has the advantages of simple principle, wide application range and good processing effect, can effectively support various most advanced digital signal processing algorithms and the like.
Description
technical field [0001] The present invention mainly relates to the field of digital signal processors that perform large-scale parallel data processing, and specifically refers to a scalable vector operation cluster, that is, a support vector compression instruction, an internally integrated tightly coupled expansion function unit, and a vector width configurable Scalable cluster of vector operations. Background technique [0002] In the current fast-developing wireless communication, video image, and radar signal processing applications, the algorithm has higher and higher requirements for the performance of the microprocessor. Aiming at the parallelism of a large amount of data in the algorithm program, the current digital signal processor structure adopts different compromise strategies in terms of flexibility, power consumption and performance, and various solutions are proposed. Such as stream processors, array processors, vector processors, etc. Imagine, a representa...
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Inventor 陈书明杨惠万江华刘衡竹郭阳孙永节刘宗林龚国辉鲁建壮许邦建刘蓬侠
Owner NAT UNIV OF DEFENSE TECH