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Non-volatile semiconductor memory device

A storage device, non-volatile technology, used in semiconductor devices, semiconductor/solid-state device manufacturing, transistors, etc., can solve problems such as high cost, reduce memory cell integration, and reduce area and power consumption. , the effect of high integration

Inactive Publication Date: 2011-04-13
SEMICON ENERGY LAB CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the disadvantage of increasing this area is that the area of ​​the memory cell required for the storage element is increased to reduce the integration of the memory cell, resulting in a higher bit cost of the non-volatile semiconductor memory device

Method used

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Examples

Experimental program
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Embodiment 1

[0054] The nonvolatile semiconductor memory device of this embodiment includes a plurality of memory cells (basic cells for storing data), a plurality of source lines, a plurality of bit lines, and a plurality of word lines arranged in a matrix. Each of the memory cells includes a storage element electrically connected to one of the source lines, one of the bit lines, and one of the word lines. In this embodiment, memory transistors are used as memory elements.

[0055] will refer to figure 1 , Figure 2A to Figure 2C , image 3 and Figure 4 A nonvolatile semiconductor memory device (hereinafter also referred to as a memory device) of this embodiment will be described. figure 1 is a plan view showing the layout of one memory cell of the memory device in this embodiment. Figure 2A to Figure 2C are respectively along figure 1 The cross-sectional view taken by the section lines A1-A2, B1-B2 and C1-C2. image 3 is a block diagram showing one example of the structure of...

Embodiment 2

[0122] This embodiment is a modified example of Embodiment 1. The memory device of this embodiment includes a memory element in which the thickness of the insulating film between the island-shaped semiconductor region and the floating gate is partially different. Refer below Figure 9 and Figure 10A to Figure 10C to describe this example.

[0123] Figure 9 is a plan view showing one example of the structure of the memory cell of this embodiment, and Figure 10A to Figure 10C are respectively along Figure 9 The cross-sectional view taken by the section line A1-A2, B1-B2 and C1-C2. The manufacturing method and structure of the memory cell of this embodiment are described below. Note that descriptions about structures similar to those in Embodiment 1 are omitted.

[0124] First, as described in Embodiment 1, the island-shaped semiconductor regions 101 and 102 are formed over the substrate 100 with the insulating film 130 interposed therebetween. Then, an insulating fil...

Embodiment 3

[0135] In this embodiment, a nonvolatile semiconductor memory device which is a modified example of Embodiment 2, which is different from Embodiment 1, will be described. The memory device of this embodiment includes a memory element in which the thickness of the insulating film between the island-shaped semiconductor region 101 and the floating gate is partially different. refer to Figure 13 and Figure 14A to Figure 14C to describe this example. Note that descriptions about structures similar to those in Embodiments 1 and 2 are omitted.

[0136] Figure 13 is a plan view of the memory cell of the memory device of this embodiment, and Figure 14A to Figure 14C are respectively along Figure 13 The cross-sectional view taken by the section line A1-A2, B1-B2 and C1-C2.

[0137] First, as described in Embodiment 2, the island-shaped semiconductor regions 101 and 102 are formed over the substrate 100 with the insulating film 130 interposed therebetween. Then, an insulatin...

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Abstract

The object of the invention is to reduce the writing and erasing voltages of a memory transistor without increasing the area of a memory cell, and to reduce the area of a memory cell without increasing the writing and erasing voltages. The memory cell includes a memory transistor having a first island-shaped semiconductor region, a floating gate and a control gate. In addition, a second island-shaped semiconductor region is formed under the floating gate with an insulating film interposed therebetween. Since the second island-shaped semiconductor region is electrically connected to the control gate, a capacitance is formed between the second island-shaped semiconductor region and the floating gate. This capacitance contributes to an increase in the coupling ratio of the memory transistor,which makes it possible to increase the coupling ratio without increasing the area of the memory cell. Furthermore, the area of the memory cell can be reduced without reducing the coupling ratio.

Description

technical field [0001] The present invention relates to a nonvolatile semiconductor memory device in which data can be written, read and erased. Background technique [0002] As a nonvolatile semiconductor memory device, EEPROM (Electrically Erasable Programmable Read Only Memory), flash memory, and the like are known. These nonvolatile semiconductor memory devices are used as recording media for various products such as digital cameras, portable audio players, and cellular phones. Research and development of nonvolatile semiconductor memory devices has been actively conducted in order to meet market needs such as further reduction in product size, increase in memory capacity, increase in speed of writing and reading data, and reduction in power consumption. [0003] As one of the ways to meet the above-mentioned market needs, in recent years, so-called SOI (silicon-on-insulator) type nonvolatile semiconductor memory devices have been actively developed, in which elements a...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/8247H01L27/115H01L29/786H01L29/788H01L29/792
CPCH01L27/12H01L29/7881H01L27/11521H01L27/11519H01L29/66825H10B41/10H10B41/30H01L29/40114
Inventor 浅见良信
Owner SEMICON ENERGY LAB CO LTD
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