Pseudo-static memory and method for controlling write operation and refresh operation of pseudo-static memory

Abstract

The invention provides a pseudo-static memory. The pseudo-static memory comprises a first register set, a second register set, a write operation buffer, a write operation flag register, a comparator and a control circuit, wherein the comparator is used for comparing a memory set address which the current write operation aims at with a memory set address in the second register set and outputting comparison result signals; the control circuit comprises a first control submodule; and the first control submodule is used for writing data in the first register set into the write operation buffer and executing the refresh operation when the write operation conflicts with the refresh operation in the current time period, setting a write state signal of the write operation flag register as a valid identification signal when the write state signal of the write operation flag register is an invalid identification signal, and writing data in the second register set into the appointed memory set when the write state signal of the write operation flag register is the valid identification signal and the comparator outputs the comparison result signals with different addresses. The pseudo-static memory can increase the access speed of a pseudo static random access memory (SRAM) so as to improve the working efficiency of the pseudo SRAM.

Description

technical field [0001] The invention relates to the technical field of memory processing, in particular to a pseudo-static memory capable of controlling write operations and refresh operations in parallel and a control method thereof, and a pseudo-static memory capable of parallel control of read / write operations and refresh operations. Background technique [0002] DRAM (Dynamic Random-Access Memory, DRAM) is a large-capacity memory. DRAM requires very few transistors in the memory array (at least a single transistor can be realized), which is very conducive to reducing area overhead. Therefore, as the system The gradual reduction of chip size has been widely used. The transistors of the DRAM can only hold data for a short time due to electric leakage. In order to keep the data, the DRAM must be refreshed (refresh) once in a while. If the memory cells are not refreshed, the stored information / data will be lost. [0003] Static Random Access Memory (SRAM) is a typical high...

AI Technical Summary

Problems solved by technology

The DRAM architecture inside the pseudo-SRAM gives it more advantages than traditional SRAM, such as smaller size, but because it uses the DRAM core, it also needs to be periodically refreshed to save data

So the problem brought at the same time is that the access speed is not as fast as the real SRAM due to refresh.

It can be seen that the access speed has become the bottleneck of the development of pseudo-SRAM memory

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