Digital background calibration circuit

Abstract

The invention discloses a digital background calibration circuit used for a high-speed and high-precision pipelined analog-to-digital converter. The digital background calibration circuit comprises a pseudo random number generator, pipelined circuits with calibration functions and a digital background calibration engine. Based on the structure of the traditional pipelined analog-to-digital converter, a primary-stage pipelined circuit and a secondary-stage pipelined circuit are modified in the circuit disclosed in the invention to realize the injection of random signals and the digital background calibration engine is used to associate the random signals so as to realize the real-time extraction and compensation of error information, thereby avoiding the influence of irrational factors of the traditional pipelined analog-to-digital converter (such as capacitor mismatching, limitations of operational amplifier gains and the like) on the conversion precision of the analog-to-digital converter. The technology can lower the design difficulty of an analog circuit and ensure the performance of a system. At the same time, because of the simple algorithm and the low implementation complexity, the calibration circuit can be used to effectively reduce the area of the chip and lower the power consumption of the system, thereby being especially applicable to a high-speed system.

Description

technical field [0001] The invention relates to a calibration circuit in the technical field of microelectronics, in particular to a digital background calibration circuit. Background technique [0002] The basic idea of ​​the pipelined A / D converter with the traditional structure is to evenly distribute the overall required conversion accuracy to each stage, and then combine the conversion results of each stage to become the final conversion result. Such as figure 1 It is the basic structure of the traditional pipeline analog-to-digital converter. The pipeline analog-to-digital converter mainly includes a sample-and-hold circuit 11 , an n-stage pipeline module 13 , and a time alignment and correction circuit 15 . Except that the last stage is a fully parallel structure, each stage of the pipeline has the same structure, consisting of an internal sample-and-hold circuit 131, a low-resolution sub-analog converter 133, a sub-digital-analog converter 135, and a margin gain ci...

AI Technical Summary

Problems solved by technology

However, non-ideal factors such as capacitance mismatch caused by process deviation and limited operational amplifier gain directly affect the performance of the analog-to-digital converter

If not calibrated, the performance of the ADC is limited to 8 to 11 bits of accuracy

Images