Data shuffling unit with switch matrix memory and shuffling method thereof

Abstract

The invention discloses a data shuffling unit with a switch matrix memory, comprising a crossbar switch, an input logic unit, an output logic unit, a main control logic unit and a switch matrix memory, wherein the main logic unit is connected with the input logic unit, and the output end of the switch matrix memory is connected with a switch selection signal end of the crossbar switch. The invention also provides a shuffling method of the data shuffling unit, when pretreatment is carried out, a shuffling request in a user program is converted into a switch matrix in the switch matrix memory, and when a shuffling instruction is executed, the main control logic unit controls to read a switch matrix corresponding to a required shuffling mode from the switch matrix memory and then further controls the crossbar switch directly to carry out data selection recombination. The data shuffling unit has the characteristics of simple structure, flexibility and high efficiency in shuffling, short time delay of key circuits and suitability for any shuffling operation.

Description

technical field [0001] The invention relates to the field of digital signal processors of SIMD technology, in particular to a data shuffling unit and a shuffling method thereof. Background technique [0002] SIMD (Single Instruction Stream Multiple Data streams) technology generally includes sub-word parallel technology and vector technology, both of which develop data-level parallelism of applications from both micro and macro directions. SIMD technology can process multiple parallel data while executing one instruction, and its high power efficiency has great advantages in solving computing-intensive applications, so it has been widely used and developed, and is favored by processors, especially DSP (Digital Signal Processor, Digital Signal Processor) of all ages. figure 1 It is a schematic diagram of a typical DSP structure using SIMD technology, which is represented by figure 1 It can be seen that the instruction fetching and decoding unit reads instructions from the p...

AI Technical Summary

Problems solved by technology

There are two problems in this scheme: 1. The process of configuring the shuffling mode register for the user is relatively inconvenient

If you configure the shuffling mode register through the control register configuration bus, it will take a lot of beats (the shuffling mode register usually has tens to hundreds of bits, while the width of the configuration bus is usually only 32 bits); if the memory access instruction will It also takes a certain number of beats to load the shuffling mode from the on-chip memory into the shuffling mode register, and because the configuration process competes with ordinary memory access requests for storage bandwidth resources, it will affect the memory access efficiency of the application; 2 . The shuffling mode needs to be decoded before entering the crossbar

The traditional shuffling unit needs to first decode the shuffling mode in the shuffling mode register to form a 01 value that controls each node switch of the crossbar to turn on or off, and then these decoded 01 values ​​drive the crossover The switch performs data selection, and the critical path delay of this process is relatively large, which is not conducive to the high frequency or scalability design of the shuffling unit

[0006] Judging from the current published literature, there are many studies on the improvement and simplification of the shuffle network itself, and there is no special literature designed to improve the configuration process of the shuffle mode.

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