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Method for applying photoresist lifting-off technology to protect photoetching alignment marks

A technology of photolithography alignment and stripping process, which is applied in the direction of photolithography, optics, and optomechanical equipment on the pattern surface, and can solve the problems affecting the shape of the front-layer lithography alignment marks, etc.

Active Publication Date: 2011-05-11
FOUNDER MICROELECTRONICS INT
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Problems solved by technology

[0005] Embodiments of the present invention provide a method for protecting photolithography alignment marks by applying a photoresist stripping process, so as to solve the problem of affecting the morphology of front layer photolithography alignment marks when covering a thick metal layer in the existing semiconductor chip manufacturing process

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  • Method for applying photoresist lifting-off technology to protect photoetching alignment marks
  • Method for applying photoresist lifting-off technology to protect photoetching alignment marks
  • Method for applying photoresist lifting-off technology to protect photoetching alignment marks

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Embodiment Construction

[0016] In view of the above-mentioned problems existing in the prior art, the embodiments of the present invention protect the photolithographic alignment marks on the front layer before covering the metal layer by applying the photoresist stripping process, so that the photolithographic alignment marks are not covered by the metal layer , so as to maintain the shape of the photolithography alignment mark, so that the photolithography machine can be aligned according to the alignment mark in the subsequent photolithography process.

[0017] Embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings.

[0018] still as in Figure 1a The substrate covered with an aluminum layer is shown as an example. When the uppermost dielectric layer of the substrate 100 needs to be covered with an aluminum layer, the embodiment of the present invention applies a photolithographic lift-off process to protect the photolithographic alignme...

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Abstract

The invention discloses a method for applying photoresist lifting-off technology to protect photoetching alignment marks, which comprises the following steps: the surface of a dielectric layer to be covered with a thick metal layer is coated with photoresist, so as to enable the zone with the photoetching alignment marks formed on the dielectric layer to be fully covered by the photoresist; the treatment for exposure and developing is performed, so as to reserve the photoresist covered on the zone with the photoetching alignment mark formed, and remove the photoresist covered on other zones; the metal layer is settled; and the photoresist covered on the zone with the photoetching alignment marks formed and the metal layer covered on the photoresist are lifted off. By adopting the invention, the shape of the photoetching alignment marks on the original layer is reserved when the metal layer is covered, so that the alignment precision during photoetching is improved.

Description

technical field [0001] The invention relates to the field of semiconductor chip manufacturing technology, in particular to a method for protecting photolithographic alignment marks by using a photoresist stripping technology. Background technique [0002] In the semiconductor chip manufacturing process, for chips used in high current and high voltage applications, it is necessary to cover thick metal layers during the chip manufacturing process. For chips that require a thick metal layer, such as DMOS (Double diffused Metal Oxide Semiconductor transistor, double diffused metal oxide semiconductor transistor) products, a thicker aluminum layer is used. However, when a thick aluminum layer covers the lithographic alignment marks left by the previous layer, it will seriously affect the morphology of the alignment marks, causing difficulties in the alignment process of the lithography machine. Such as Figure 1a and Figure 1b as shown, Figure 1a It is a schematic diagram of ...

Claims

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Application Information

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IPC IPC(8): H01L21/02H01L23/544G03F7/00
Inventor 马万里赵文魁
Owner FOUNDER MICROELECTRONICS INT
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