No-wire bonding packaging method and finished products of power semiconductor chip

Abstract

The invention discloses a no-wire bonding packaging method and no-wire bonding packaging finished products of a power semiconductor chip. The method comprises the following steps of: forming a first conducting layer, namely forming the first conducting layer with a joint part of a positive electrode and a negative electrode on a carrier; bonding a chip, namely bonding a positive electrode and a negative electrode of the semiconductor chip on the joint part of the positive electrode and the negative electrode by using a conduction piece respectively; bonding a reflecting layer as required, namely bonding a wire frame on a first conducting layer, wherein the wire frame is bonded on the circumference of the semiconductor chip so as to form a chamber of which the inner circumference is provided with a reflecting surface; packaging and molding, namely filling transmitting package materials into the circumference of each semiconductor chip; and forming a second conducting layer, namely at least forming a matched second conducting layer corresponding to the position of each semiconductor chip. Therefore, the method is suitable for packaging requirements of different arrangement forms, effectively simplifies processing programs and reduces production cost.

Description

Technical field: [0001] The invention relates to a wire-free packaging method for power semiconductor chips and its finished products, especially to a chip-free packaging method suitable for two types of arrangements, such as flip-chip (FLIP-CHIP) and wire-bond (WIRE-BOND). Wire bonding packaging method and finished product. Background technique: [0002] As we all know, the packaging methods of various chips have a great influence on their heat dissipation effect. The traditional chip (such as: LED) packaging method is to solder the bottom of the chip to a packaging base in a crystal bonding manner, and then use gold wires to connect it. The positive and negative poles are connected to the positive and negative pins respectively. The heat conduction route of this package structure is long, and the heat conduction area of ​​the gold wire is limited, which affects its overall heat dissipation effect and makes it unable to exert its maximum power (luminous intensity). [0003...

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Problems solved by technology

[0004] However, although the FLIP-CHIP chip packaging structure disclosed in the above-mentioned patent can improve the heat conduction efficiency and obtain a better heat dissipation effect, the light needs to pass through the transparent substrate to radiate outward, which will affect its performance. Luminous efficiency forms a deficiency in application. Therefore, compared with the traditional WIRE-BOND arrangement type chip packaging structure, both have their own advantages and disadvantages, and cannot completely replace each other; moreover, due to the case The disclosed processing method is only for the chip packaging structure of the inverted chip (FLIP-CHIP) arrangement, and cannot be applied to the chip packaging structure of the traditional wire bonding (WIRE-BOND) arrangement type. Therefore, in terms of the current chip packaging method , the traditional WIRE-BOND arrangement is completely different from the flip-chip (FLIP-CHIP) arrangement. The chip packaging method is completely different, and the overall process planning and equipment settings are also different and cannot be shared. In this way, not only It causes inconvenience in production, and it is also difficult to effectively reduce its production cost

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