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Method for performing instruction optimization on column confusion process in advanced encryption standard (AES) encryption algorithm and instruction set processor

An encryption algorithm and process instruction technology, applied in concurrent instruction execution, electrical digital data processing, instruments, etc., can solve the problems of occupying a lot of hardware resources, difficult to combine, and limited acceleration effect.

Inactive Publication Date: 2014-07-23
SHANDONG UNIV
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0013] The first method actually optimizes the algorithm itself, but there is an optimization bottleneck and the acceleration effect is limited; the second method uses hardware acceleration, although the acceleration effect is more obvious, but this optimization method has weak scalability. It occupies relatively more hardware resources, and it is relatively difficult to combine with other modules in the program; the third method not only reduces the execution code space and improves the execution speed of the algorithm, but also in the design It is easy to implement, has strong flexibility, and requires much less hardware resources than the first method, which is suitable for small-scale circuits.

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  • Method for performing instruction optimization on column confusion process in advanced encryption standard (AES) encryption algorithm and instruction set processor
  • Method for performing instruction optimization on column confusion process in advanced encryption standard (AES) encryption algorithm and instruction set processor
  • Method for performing instruction optimization on column confusion process in advanced encryption standard (AES) encryption algorithm and instruction set processor

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Embodiment Construction

[0075] The present invention will be further described below in conjunction with the accompanying drawings and embodiments.

[0076] Figure 5 In , some steps of the column obfuscation process are accelerated under the premise of not changing the length of the instruction opcode, the number of instruction bits, and not affecting the running speed of the processor. The specific process is as follows:

[0077] 1) When performing the AES encryption / decryption algorithm column obfuscation operation, the position of the data in the matrix needs to be positioned multiple times during the matrix multiplication operation, that is, the data at the position of matrix[i][j] is taken out. The data of the matrix in the actual memory is stored linearly, so in the traditional ARM processor, it is necessary to calculate the offset position of the data in the actual memory according to i and j, and search based on the offset position based on the base address matrix data, so 6 assembly...

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Abstract

The invention relates to a method for performing instruction optimization on a column confusion process in an advanced encryption standard (AES) encryption algorithm and an instruction set processor. Three new extended instructions are designed to accelerate the column confusion process in the AES encryption algorithm. The three new extended instructions comprise (1) matrixpos(dest)=(src1), (src2), (src3), (src4), used for accelerating matrix bitwise operation in the column confusion process, (2) xor4(dest)=(src1), (src2), (src3), (src4), used for accelerating quaternary XOR operation in the column confusion process, and (3) xor_move(src1), (src2), (src3), (src4), (src0), used for accelerating intra-domain multiplication operation in the column confusion process. The three new extended instructions are finished within one clock period. In the traditional advanced reduced instruction set computer (RISC) machine (ARM) processor, the instructions need a plurality of clock periods respectively, so the new instructions have the accelerating effect. The invention designs a special instruction processor model, namely MASIP corresponding to a new instruction set. The processor model realizes the extended instructions on the basis of hardware logic, so the processor model specially aims to accelerate the column confusion process in the AES encryption algorithm.77

Description

technical field [0001] The invention relates to the encryption and decryption technology of AES, in particular to a column confusion process instruction optimization method in the AES encryption algorithm and an instruction set processor thereof. Background technique [0002] AES is the abbreviation of The Advanced Encryption Standard (Advanced Encryption Standard). It is a specification for encrypting electronic data published by the National Institute of Standards and Technology (NIST). It is the most widely used block cipher algorithm. The AES algorithm adopts a symmetric block cipher system, the key length can be 128 bits, 192 bits, and 256 bits respectively, and the block length is fixed at 128 bits. [0003] The AES encryption process encrypts the original text in units of rounds, and each round mainly includes the following four processes: (1) Byte replacement (SubBytes), which looks up the table according to the generated Sbox, and replaces the original text with C...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F9/30G06F9/318G06F9/38
Inventor 李沂滨贾智平李新陈仁海陈健
Owner SHANDONG UNIV
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