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Method for making shallow trench isolation structure

A technology of isolation structure and manufacturing method, which is applied in the field of manufacturing shallow trench isolation structures, can solve the problems of uneven surface of insulating oxide layer and affect the reliability of devices, etc., and achieve the effect of increased density and smooth surface

Inactive Publication Date: 2011-06-15
SEMICON MFG INT (SHANGHAI) CORP +1
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Problems solved by technology

[0009] However, due to the different gas flow ratios used in the three-step deposition of the high aspect ratio process, the shrinkage ratio of the insulating oxide layer filled in three steps will also be different after the annealing process at the end of the deposition, which will cause the insulating oxide layer after filling The surface is uneven. After the chemical mechanical polishing process, a depression with a depth greater than 230 angstroms will be generated on the shallow trench isolation structure. This defect will be amplified by the subsequent acid bath etching process, thereby affecting the reliability of the device.

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  • Method for making shallow trench isolation structure
  • Method for making shallow trench isolation structure
  • Method for making shallow trench isolation structure

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Embodiment Construction

[0024] When forming a shallow trench isolation structure in the prior art, due to the different gas flow ratios used in the three-step deposition of the high aspect ratio process, the shrinkage ratio of the insulating oxide layer filled in three steps will also be different after the deposition is completed and the annealing process is performed. , It will cause the surface of the insulating oxide layer after filling to be uneven, and the shallow trench isolation structure will have a depth of more than 230 angstroms after the chemical mechanical polishing process, which will cause the reliability of the device to deteriorate.

[0025] The present invention improves the process, and the specific process is as Figure 4 As shown, step S101 is performed to provide a semiconductor substrate with a pad oxide layer and an etching barrier layer formed in sequence, wherein a shallow trench is formed in the semiconductor substrate; step S102 is performed to form a liner oxide layer on the ...

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Abstract

The invention discloses a method for making a shallow trench isolation structure, which comprises the following steps of: providing a semiconductor substrate on which a pad oxide layer and a corrosion blocking layer are sequentially formed, wherein a shallow trench is formed in the semiconductor substrate; forming a lining oxide layer on the inner wall of the shallow trench; fully filling a firstinsulating oxide layer and a second insulating oxide layer into the shallow trench; performing an annealing process; filling a third insulating oxide layer into the shallow trench to the predetermined height; and removing the corrosion blocking layer and the pad oxide layer to form the shallow trench isolation structure. Hollowness generated on the shallow trench isolation structure is extremely small, and the depth of the hollowness is less than 50 angstroms, so the performance of a semiconductor device is not affected.

Description

Technical field [0001] The invention relates to the manufacturing field of semiconductor devices, in particular to a manufacturing method of a shallow trench isolation structure. Background technique [0002] As the size of integrated circuits decreases, the devices that make up the circuit must be placed more densely to accommodate the limited space available on the chip. As current research is devoted to increasing the density of active devices per unit area of ​​a semiconductor substrate, effective insulation between circuits becomes more important. [0003] Shallow trench isolation (STI) technology has a number of process and electrical isolation advantages, including reducing the area occupied on the wafer surface while increasing the integration of the device, maintaining surface flatness and reducing channel width erosion. Therefore, at present, most of the active area isolation layers of MOS circuits, for example, the active area isolation layer of the components below 0.1...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/762
Inventor 李敏
Owner SEMICON MFG INT (SHANGHAI) CORP
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