Method for realizing cache coherence protocol of chip multiprocessor (CMP) system

A multi-core processor and processor system technology, applied in the field of cache coherence protocol implementation, can solve problems such as inability to complete write operations, and achieve the effects of avoiding starvation, improving performance, reducing power consumption and bandwidth usage

Active Publication Date: 2011-06-22
INST OF COMPUTING TECH CHINESE ACAD OF SCI
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Problems solved by technology

In this way, all requesters can get the data, but none of them can complete the write operation to it

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  • Method for realizing cache coherence protocol of chip multiprocessor (CMP) system
  • Method for realizing cache coherence protocol of chip multiprocessor (CMP) system
  • Method for realizing cache coherence protocol of chip multiprocessor (CMP) system

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Embodiment Construction

[0059] The present invention will be described in detail below in conjunction with the accompanying drawings and specific embodiments, but not as a limitation of the present invention.

[0060] Such as Figure 7 As shown, it is a structure diagram of eight processor cores with one-way slotted ring connection CMP. This structure is a one-way slotted ring connected to the on-chip multi-core processor structure used in the implementation of the protocol. Figure 7 In , the CMP composed of 8 processor cores is taken as an example to illustrate the structure, P1 to P8 represent 8 processors, and the Cache is divided into two levels of structure, namely the first-level Cache (L1) and the second-level Cache (L2). L1 is divided into instruction cache (L1I) and data cache (L1D), which are private to each processor. L2 is physically distributed among all processors and logically shared by each processor. The one-way slotted ring includes a request information ring and a data informat...

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Abstract

The invention discloses a method for realizing a cache coherence protocol of a chip multiprocessor (CMP) system, and the method comprises the following steps: 1, cache is divided into a primary Cache and a secondary Cache, wherein the primary Cache is a private Cache of each processor in the processor system, and the secondary Cache is shared by the processors in the processor system; 2, each processor accesses the private primary Cache, and when the access fails, a failure request information slot is generated, sent to a request information ring, then transmitted to other processors by the request information ring to carry out intercepting; and 3, after a data provider intercepts the failure request, a data information slot is generated and sent to a data information ring, then transmitted to a requestor by the data information ring, finally, the requestor receives data blocks and then completes corresponding access operations. The method disclosed by the invention has the advantages of effectively improving the performance of the system, reducing the power consumption and bandwidth utilization, avoiding the occurrence of starvation, deadlock and livelock, and improving the stability of the system.

Description

technical field [0001] The invention relates to a microprocessor, in particular to a method for realizing a high-speed cache (Cache) coherence protocol of an on-chip multi-core processor (Chip Multiprocessor, CMP) system. Background technique [0002] In the shared storage CMP system, multiple versions of the same data may exist in the memory and the Cache of multiple processors at the same time. If multiple processors write the data at this time, data inconsistency may occur , resulting in an error in program execution. The Cache coherence protocol is a mechanism for ensuring data consistency in the Cache of each processor in a multiprocessor system, and is a key factor affecting the correctness, performance, power consumption and bandwidth of the system. Protocols can be implemented by software or hardware methods. The present invention is a Cache coherence protocol realized by hardware method, and the following protocols all refer to protocols realized by hardware. [...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F15/167G06F15/173
Inventor 曹非刘志勇
Owner INST OF COMPUTING TECH CHINESE ACAD OF SCI
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