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Fabrication method of shallow trench isolation (STI) structure

A technology of isolation structure and manufacturing method, which is applied in the field of manufacturing shallow trench isolation structures, can solve problems such as the degradation of semiconductor device quality and the isolation characteristics of shallow trench isolation structures, and achieve improved yield, improved electrical performance, and high-level Reduced effect

Active Publication Date: 2011-07-13
SEMICON MFG INT (SHANGHAI) CORP +1
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

A large step height will generate leakage current and reduce the isolation characteristics of the shallow trench isolation structure, resulting in a decrease in the quality of the final formed semiconductor device

Method used

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  • Fabrication method of shallow trench isolation (STI) structure
  • Fabrication method of shallow trench isolation (STI) structure
  • Fabrication method of shallow trench isolation (STI) structure

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Embodiment Construction

[0020] The inventors have found that when making shallow trench isolation structures, since the etch rate of the silicon nitride layer is greater than the etch rate of the filling oxide layer (material is silicon oxide), the silicon nitride layer and pad oxide are removed. After the layer, the step height of the shallow trench isolation structure is relatively large, which will cause leakage current and reduce the isolation characteristics of the shallow trench isolation structure, thereby leading to a decrease in the electrical performance of the semiconductor device.

[0021] Therefore, in the manufacture of semiconductor devices, in order to prevent the above-mentioned defects from affecting the product yield. The invention provides a method for manufacturing a shallow trench isolation structure, comprising: providing a semiconductor substrate, on which a pad oxide layer, a silicon nitride layer, and a shallow trench are sequentially formed; forming a substrate oxide layer ...

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Abstract

The invention provides a fabrication method of a shallow trench isolation (STI) structure. The method comprises the following steps: providing a semiconductor substrate, and sequentially forming a pad oxide layer, a silicon nitride (SiN) layer and a shallow trench on the semiconductor substrate; forming a substrate oxide layer in the shallow trench; forming a filling oxide layer for filling up the shallow trench on the substrate oxide layer; removing part of the filling oxide layer until the SiN layer is exposed; implanting nitrogen ions into the filling oxide layer; removing the SiN layer and part of the filling oxide layer implanted with the nitrogen ions; and removing the pad oxide layer. By utilizing the fabrication method, the removal rate of the filling oxide layer containing the nitrogen ions is increased so that step height of the STI structure is reduced, thus enhancing the electrical properties of semiconductor devices and improving the yield of semiconductor products.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a manufacturing method of a shallow trench isolation structure. Background technique [0002] The development direction of semiconductor integrated circuits is to increase density and shrink components. The shallow trench isolation structure is used to isolate devices formed on a silicon substrate from other devices. With the advancement of semiconductor manufacturing technology, shallow trench isolation (Shallow Trench Isolation, STI) technology has gradually replaced other isolation methods such as local oxidation of silicon (LOCOS) used in traditional semiconductor device manufacturing. [0003] Figure 1 to Figure 4 , shows a schematic diagram of the process of fabricating a shallow trench isolation structure using an existing fabrication method. The existing manufacturing method includes: firstly, oxidizing a silicon wafer in a high-temperature oxidatio...

Claims

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Application Information

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IPC IPC(8): H01L21/762
Inventor 何永根陈勇
Owner SEMICON MFG INT (SHANGHAI) CORP