Test structure and test method for coupling capacitance of metal redundant fillers in integrated circuit

Abstract

The invention relates to a test structure and a test method for coupling capacitance of metal redundant fillers in an integrated circuit. In the process of manufacturing the integrated circuit, redundant metal is often filled into a layout to improve the planarization effect, but the coupling capacitance is influenced by the redundant metal greatly. Therefore, based on the condition, the invention provides a test structure for the coupling capacitance of the metal redundant fillers and a test method using the test structure. The test structure comprises test metal layers formed by media, a copper wire array to be tested, peripheral leads and test pins. In the test structure, the coupling capacitance of the metal redundant fillers can be measured effectively by the multi-layer test structure, the influence on the coupling capacitance can be compared for different types of metal redundant filling structures, and the measurement of multilayer interconnection wires can be simplified by arranging the metal redundant fillers for improving the chemical mechanical planarization (CMP) effect in a coupling capacitance actual test structure additionally and selecting the test structure of anappropriate size and designing a special pin and lead structure.

Description

technical field [0001] The invention relates to the technical field of integrated circuit manufacturing technology and layout design, in particular to a testing structure and method for coupling capacitors of integrated circuit metal redundant fillers. Background technique [0002] The integrated circuit (Integrated Circuit, IC) manufacturing technology develops at a speed of doubling the integration level every 18 months according to Moore's Law. As device feature sizes shrink, the effects of parasitic parameters become more pronounced. Parasitic parameters are essentially caused by the introduction of a new circuit structure. For example, if a metal line is placed next to another metal line, there will be parasitic effects. Especially in the current circuit with relatively high frequency and high wiring density, the problem of parasitic effects seriously affects the timing convergence and signal integrity of the circuit. Therefore, in the process of integrated circuit de...

AI Technical Summary

Problems solved by technology

However, there are many defects in the use of EDA tool software. For example, the internal circuit model of the software is complex, and it takes a lot of simulation and calculation time for the layout of complex structures, and there is a certain degree of error between the simulation results and the actual values.

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