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IC (integrated circuit) function verification method

A function verification and normalization technology, applied in special data processing applications, instruments, electrical digital data processing, etc., can solve the problem of memory space explosion, no way to measure function coverage, function coverage cannot be effectively guaranteed, etc. question

Inactive Publication Date: 2011-08-10
李姮乐
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Problems solved by technology

However, this method depends on the quality of the random vector generation algorithm on the one hand, and has certain requirements on the number of verification vectors on the other hand, for example, it cannot cause memory space explosion, etc., so the achievable functional coverage is often not obtained. effective guarantees, and there is no way to measure the functional coverage achieved by the generated vectors

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  • IC (integrated circuit) function verification method
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Embodiment Construction

[0044] According to the scheme technical route architecture of the method of the present invention, the following will be further described in detail in conjunction with specific embodiments. The specific embodiments described here are not limitations of the present invention, but explanations of the present invention. The specific implementation methods are as follows: the process is as follows image 3 shown.

[0045]1. Unify the internal register configuration information and external interface timing of the design under test into a normalized timing diagram.

[0046] The key to this step is to incorporate the internal register configuration into the timing diagram of the external interface.

[0047] What we know is the interface timing diagram reflecting its external characteristics and the configuration information of registers reflecting its internal state in the interface specification of the module to be tested. In order to achieve unification, we hope to incorporate ...

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Abstract

The invention provides an IC (integrated circuit) function verification method. The method comprises the following steps: based on an interface sequence diagram reflecting external characteristics of a module to be tested and configuration information of an internal register reflecting the internal state of the module to be tested in design specifications of the module to be tested, establishing a finite-state machine model, then traversing the state of the finite-state machine model, simultaneously adding loop parameter setting to a directed circuit and a critical path more concerned by a user, thereby realizing a higher function coverage rate. The method has the ultimate goal of obtaining more function verification coverage with less verification vectors, thereby improving verification working efficiency, reducing verification cost, improving design reliability and shortening the marking time of products.

Description

technical field [0001] The invention relates to the field of design and verification of large-scale digital integrated circuits, in particular to a method for verifying functions of large-scale integrated circuits. Background technique [0002] At present, IC functional verification methods include static verification and dynamic verification. [0003] Static verification mainly refers to formal verification, which proves the equivalence between the design target and the module to be tested by means of mathematical methods. It does not need to inject stimulus and can give complete coverage, but it cannot replace analog simulation, because it can only be applied to small-scale designs under current technology conditions. [0004] Dynamic verification refers to the verification method based on simulation. There are two main methods used now: vector exhaustion method and random vector generation method. Example of vector exhaustive method figure 1 , it checks the correctness...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F17/50
Inventor 苏世祥连志斌孙钊谢峥
Owner 李姮乐
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