Clock frequency multiplier, device and clock frequency multiplication method

Abstract

The invention discloses a clock frequency multiplier, a clock frequency multiplication device and a clock frequency multiplication method. The clock frequency multiplier comprises a pulse generator, a phase shifter, a phase synthesizer and a frequency divider, wherein the pulse generator is used for regulating an external input clock signal into an equal periodic pulse clock signal; the phase shifter is used for performing phase shifting on the input equal periodic pulse clock signal for different time lengths according to a required frequency multiplication fold and a clock cycle to obtain phase shifted clock signals; the phase synthesizer is used for performing phase synthesis on the equal periodic pulse clock signal and each phase shifted clock signal to obtain a frequency multiplied clock signals; and the frequency divider is used for performing frequency division on the phase-synthesized frequency multiplied clock signal to obtain a frequency multiplied output clock signal, and outputting the frequency multiplied output clock signal. By the clock frequency multiplier, the clock frequency multiplication device and the clock frequency multiplication method, the frequency multiplication of the clock signal is realized under the condition of no phase-locked loops, and / or normal operations can be realized under the condition of radiation exposure.

Description

technical field [0001] The invention belongs to integrated circuits of frequency synthesizers, in particular to a clock multiplier and device and a clock frequency multiplication method, more specifically to a clock multiplier and device and a clock for anti-irradiation integrated circuits Doubling method. Background technique [0002] At present, clock frequency multipliers are widely used in integrated circuits. In the prior art, a phase-locked loop (PLL) is generally used as a clock frequency multiplier to increase the frequency of an input clock signal. However, the structural design of the phase-locked loop is too complicated and the stability is poor, and the anti-irradiation performance of the entire phase-locked loop loop is poor, and errors are prone to occur under radiation exposure conditions. [0003] Moreover, most of the existing frequency multiplication technologies use counters or shift registers as the state memory. When this state memory encounters radiati...

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Problems solved by technology

However, the design of the PLL structure is too complicated and the stability is poor, and the anti-radiation performance of the entire PLL loop is poor, and errors are prone to occur under radiation exposure conditions.

[0003] Moreover, most of the existing frequency multiplication technologies use counters or shift registers as state memory. When this state memory encounters radiation exposure, the flip-flops in it may flip, resulting in logic errors, so that the final The period of the clock output signal changes

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