Manufacturing method of EDMOS (Extended Drain Metal Oxide Semiconductor) device

Abstract

The invention relates to a manufacturing method of an EDMOS (Extended Drain Metal Oxide Semiconductor) device, wherein a process of depositing a pseudo grid structure on a semiconductor substrate above an EDMOS device drain extension area takes the place of a traditional process of depositing a salicide block (SAB) layer and a source / drain ion implant block layer, thus a breakdown voltage of the EDMOS device is increased. By utilizing the manufacturing method of the EDMOS, EDMOD devices sharing the drain can be further manufactured and have the advantages that the isolation among the devices becomes simpler and the structure extension is convenient. According to the manufacturing method of the EDMOS disclosed by the invention, the layout is simple; the operating errors generated in the manufacturing process of the EDMOS device, in which the distance between the drain and the grid is smaller than 2 microns, due to depositing of the SAB layer and source / drain ion implant block layer are effectively reduced; and the yield of the manufactured EDMOS devices is increased.

Description

Technical field [0001] The present invention relates to the field of semiconductor technology, and more specifically, the present invention relates to a manufacturing method of an Extended Drain Metal Oxide Semiconductor (EDMOS) device. Background technique [0002] MOS high-voltage devices have a wide range of applications in chips such as LCD panel drive, power management, and DC / AC converters. Evaluating the performance of high-voltage devices generally includes three indicators: breakdown voltage, on-resistance, and switching speed; evaluating the reliability of high-voltage devices generally includes two indicators: safe working area and performance degradation caused by hot electron injection. [0003] The type of MOS device used in semiconductor devices is an N or P-channel drain extended metal oxide semiconductor (EDMOS) device, which utilizes a drain extension region to increase the operating voltage of the device, and is usually used in, for example, power conversion circ...

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Problems solved by technology

[0005] In practice, it has been found that in the prior art method of manufacturing EDMOS devices, the layout is complicated during the deposition of the silicide barrier layer and the source / drain ion implantation barrier layer, and it is difficult to implement the self-alignment process, and there are operational errors in actual operation. When the distance from the drain to the gate is less than 2um, especially when the distance from the drain to the gate is less than 1um, this error will dominate and seriously affect the yield of the manufactured EDMOS devices

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