Making method for MOS (Metal Oxide Semiconductor) transistor

Abstract

The invention provides a making method for a MOS (Metal Oxide Semiconductor) transistor. The making method comprises the following steps: providing a semiconductor substrate on which a gate structure is formed; forming a liner oxidation layer on the semiconductor substrate and the gate structure; forming a clearance wall dielectric layer on the liner oxidation layer; performing plasma treatment on the clearance wall dielectric layer; and repeating the formation process of the clearance wall dielectric layer and the formation process of the plasma treatment for at least one time until the accumulated thickness of the clearance wall dielectric layer reaches the target thickness. The making method for the MOS transistor provided by the invention reduces the thickness deviation of the MOS transistor clearance walls in different areas of the thickness of the devices on the semiconductor substrate, thus consistency in effective trench lengths of the MOS transistors can be improved and consistency in the performances of the MOS transistors can be further improved.

Description

technical field [0001] The present invention relates to the technical field of semiconductors, and more specifically, the present invention relates to a manufacturing method of a MOS transistor. Background technique [0002] With the continuous advancement of integrated circuits, that is, IC technology, the number of components integrated on the same chip has evolved from the initial tens of hundreds to the present millions. The performance and complexity of current ICs are far beyond what could have been imagined at the beginning. In order to meet the requirements of complexity and circuit density (ie: the number of devices integrated into a certain area), the minimum feature size, which is known as the "geometric line width" of the device, is getting smaller and smaller with the innovation of process technology. Today, the minimum line width of MOS transistors is less than 65 nanometers. [0003] With the continuous reduction of the minimum line width of MOS transistors,...

AI Technical Summary

Problems solved by technology

For MOS transistors, the effective channel length is an important factor determining its threshold voltage and saturated source-drain current, especially for MOS transistors with a channel length below 65 nanometers, the effective channel length is very small, if the effective channel length is longer A wide range of deviations will inevitably cause large deviations in the performance of MOS transistor devices

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