Method of forming gate stack and structure thereof

Abstract

Embodiments of the present invention provide a method of forming gate stacks for field-effect-transistors. The method includes forming a metal-containing layer directly on a first titanium-nitride (TiN) layer, the first TiN layer covering areas of a semiconductor substrate designated for first and second types of field-effect-transistors; forming a capping layer of a second TiN layer on top of the metal-containing layer; patterning the second TiN layer and the metal-containing layer to cover only a first portion of the first TiN layer, the first portion of the first TiN layer covering an area designated for the first type of field-effect-transistors; etching away a second portion of the first TiN layer exposed by the patterning while protecting the first portion of the first TiN layer, from the etching, through covering with at least a portion of thickness of the patterned metal-containing layer; and forming a third TiN layer covering an areas of the semiconductor substrate designated for the second type of field-effect-transistors.

Description

[0001] Cross References to Related Applications [0002] This application claims priority to US Patent Application Serial No. 12 / 348,332, filed January 5, 2009 in the US Patent and Trademark Office, which is hereby incorporated by reference in its entirety. technical field [0003] The present invention relates to the field of semiconductor device fabrication. In particular, the present invention relates to the formation of gate stacks and structures for high-k metal gate field effect transistors. Background technique [0004] In the field of semiconductor device manufacturing, active semiconductor devices are typically fabricated by front-end-of-line (FEOL) technology. Such active semiconductor devices may include, for example, transistors such as field effect transistors (FETs) and in particular complementary metal oxide semiconductor field effect transistors (CMOS-FETs). Among the different types of CMOS-FETs, there may be p-type doped CMOS-FETs (PFETs) and n-type doped...

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Problems solved by technology

However, when a high concentration ammonia solution is able to penetrate the barrier silicon oxide for the purpose of patterning the underlying amorphous silicon, it is believed to be a source of defects in the silicon, such as causing impurities to be etched out of the silicon, resulting in defects produced by the process. degradation of the device into

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