static random access memory formed on soi substrate

A static random access and memory technology, applied in static memory, instruments, electrical solid devices, etc., can solve the problem of SRAM cell bit line metal layers and other problems

Active Publication Date: 2011-12-28
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Abstract
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Problems solved by technology

[0008] The technical problem to be solved by the present invention is to provide a static random access memory formed on a

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  • static random access memory formed on soi substrate
  • static random access memory formed on soi substrate
  • static random access memory formed on soi substrate

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[0022] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0023] The static random access memory formed on the SOI substrate provided by the present invention can be implemented in a variety of alternative ways. The following is a description of a preferred embodiment. Of course, the present invention is not limited to this specific embodiment. The general substitutions well-known to those of ordinary skill in this section are undoubtedly covered by the protection scope of the present invention.

[0024] Secondly, the present invention is described in detail using schematic diagrams. When describing the embodiments of the present invention, for convenience of description, the schematic diagrams are not partially enlarged according to a general scale and should not be used as a l...

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Abstract

The static random access memory formed on the silicon-on-insulator substrate of the present invention adopts an SOI substrate, and the drains of the first pull-up transistor (PU-1) and the first pull-down transistor (PD-1) pass through the SOI The first connection active region SL-1 of the substrate is connected, and the first connection active region SL-1 is connected with the source of the first transfer gate transistor (PG-1); the second pull-up transistor (PU- 2) It is connected with the drain of the second pull-down transistor (PD-2) through the second connection active area SL-2 of the SOI substrate, and the second connection active area SL-2 is connected with the second transfer gate transistor (PD-2) at the same time. The sources of PG-2) are connected to each other without using the first metal layer to realize the interconnection of each transistor, thereby saving one metal layer.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a static random access memory formed on a silicon-on-insulator substrate. Background technique [0002] Usually, the storage unit of SRAM (Static Random Access Memory) consists of two pull-down transistors (also called drive transistors), two pull-up transistors (also called load transistors) and two transfer gate transistors (also called transfer transistors, access transistors, active transistors). [0003] Such as figure 1 As shown, the circuit of a conventional SRAM memory cell in figure 1 shown in . In the storage unit 100, the two pull-up transistors (PU-1, PU-2) 110, 115 are PMOS transistors, and the two pull-down transistors (PD-1, PD-2) 120, 125 are NMOS transistors, thus forming two The flip-flop circuit of the cross-latch CMOS inverter, so that the memory cell 100 has two stable states for representing "0" and "1", two pass-gate transistors (PG-...

Claims

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Application Information

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IPC IPC(8): G11C5/06H01L27/12
Inventor 胡剑
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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