Condition-precharged sense-amplifier-based flip flop

Abstract

The invention discloses a condition-precharged sense-amplifier-based flip flop and relates to the technical field of integrated circuits. The condition-precharged sense-amplifier-based flip flop comprises a sense-amplifier-based flip flop (SAFF), wherein the SAFF also comprises XNOR consisting of a seventh N-channel metal oxide semiconductor (NMOS) transistor MN7 and an eighth NMOS transistor MN8, a fifth P-channel metal oxide semiconductor (PMOS) transistor MP5 and a sixth PMOS transistor MP6; the output signal node of the XNOR is X; the first end of the fifth PMOS transistor MP5 is connected with one end of a first PMOS transistor MP1; the second end of the fifth PMOS transistor MP5 is connected with a power wire; the third end of the fifth PMOS transistor MP5 is connected with the node X; the first end of the sixth PMOS transistor MP6 is connected with one end of a second PMOS transistor MP2; the second end of the sixth PMOS transistor MP6 is connected with a power wire; and the third end of the sixth PMOS transistor MP6 is connected with the node X. The condition-precharged sense-amplifier-based flip flop can increase operating speed of the circuit and can reduce energy consumption of the circuit simultaneously.

Description

technical field [0001] The invention relates to the technical field of integrated circuits, in particular to a conditional precharge trigger based on a sense amplifier. Background technique [0002] With the development of integrated circuits and the increase of portable products, the circuit system puts forward higher requirements for the reduction of power consumption. Often in a large-scale digital integrated circuit, the clock system accounts for 25% to 40% of the total chip energy consumption or even higher. About 90% of the energy consumption generated by the clock system comes from the flip-flop part and the last-level branch driving the flip-flop in the clock network (see literature [1]). Therefore, reducing the power consumption of the clock network and flip-flop plays a vital role in reducing the power consumption of the entire circuit system. One reason for the high power consumption of the clock network is that its node hopping rate reaches 100%, while the hopp...

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Problems solved by technology

[0022] The technical problem to be solved by the present invention is how to increase the operating speed of the circuit while reducing the energy consumption of the circuit

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