Method for manufacturing structure of semiconductor device for forming structure of dual damascene

Abstract

The invention provides a method for manufacturing the structure of a semiconductor device for forming the structure of a dual damascene, which comprises the steps of: providing a front-end device structure; sequentially forming a first metal layer, an etching stopping layer, a second metal layer and a first photoresist layer provided with a first opening pattern on the surface of an intermetallic dielectric layer; firstly etching till that the surface of the etching stopping layer is exposed; removing the first photoresist layer; forming a bottom anti-reflection layer; forming a second photoresist layer with a second opening pattern, wherein the second opening pattern is arranged right above an opening in the second metal layer; secondarily etching till that the surface of the intermetallic dielectric layer is exposed; removing the second photoresist layer and the bottom anti-reflection layer; and thirdly etching till that the surface of the front-end device structure is exposed. Due to the adoption of the method, the bottom anti-reflection coat (BARC)-filling quality can be improved, and the bad influence to a compact disc (CD) caused by overlong BARC etch back time can be avoided.

Description

technical field [0001] The present invention relates to the field of semiconductor manufacturing, and in particular, to a method for fabricating a semiconductor device structure for forming a dual-damascene structure. Background technique [0002] With the highly integrated semiconductor devices of integrated circuits, the surface of the chip cannot provide enough area for fabricating interconnection structures. In order to meet the increasing requirements of interconnect structure with the shrinking of complementary metal-oxide-semiconductor field-effect transistor (CMOS) device size, the manufacturing process of integrated circuit has to adopt dual damascene process. Also, currently, a multilevel interconnection structure having a three-dimensional structure is used in a deep submicron process, and an intermetal dielectric (IMD) is used to insulatively separate each interconnection structure from each other. Specifically, the dual damascene process refers to the formation...

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Problems solved by technology

[0013] However, as mentioned above, since the BARC 106 in the via hole 104 needs to be etched back for a long time in the via-first scheme, it is easy to have a bad influence on the critical dimension (CD) of the trench, resulting in the fabricated double The cross-sectional morphology of the trench in the Damascene structure is not good, and in the process of removing BARC 106, it is easy to cause damage to the IMD 103, which increases its k value, resulting in poor overall electrical properties of the final semiconductor device

Moreover, as the CD continues to shrink, the aspect ratio (aspect ratio) of the via increases, and it is easy to generate voids in the BARC when filling it.

[0014] In addition, if the trench-first scheme is adopted and PR is used as a mask to form via holes, a thicker PR is also required, and the process window will become smaller as the CD shrinks, making it difficult to control the process well.

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