Method for manufacturing complementary metal oxide semiconductor (CMOS) element

Abstract

The invention discloses a method for manufacturing a complementary metal oxide semiconductor (CMOS) element with a high dielectric constant dielectric layer and a metal grid. The method comprises the following steps of: forming an isolation structure in a substrate to define type 1 and type 2 metal oxide semiconductor regions; sequentially forming an interface layer and the high dielectric constant dielectric layer on the substrate; respectively forming first and second coverage layers on the high dielectric constant dielectric layer of the type 1 and the type 2 metal oxide semiconductor regions; respectively forming first and second grid stacked structures on partial first and second coverage layers; and performing in situ wet etching, namely etching the first and the second coverage layers sequentially by using a first etchant, and etching the interface layer and the high dielectric constant dielectric layer by using a second etchant till the substrate is exposed, wherein the second etchant is a mixed etchant containing the first etchant.

Description

technical field [0001] The invention relates to a manufacturing method of a complementary metal oxide semiconductor device, and in particular to a manufacturing method of a complementary metal oxide semiconductor device with a high dielectric constant dielectric layer and a metal gate. Background technique [0002] As the size of complementary metal-oxide-semiconductor (CMOS) components continues to shrink, traditional component film layers will also encounter many challenges. New component materials will be a problem that needs to be solved in the development of very large-scale integrated circuits (VLSI) in the next few years. . In recent years, the technical development of high-k dielectric layers and metal gates has become one of the most important researches in the semiconductor industry. [0003] Figure 1A to Figure 1E A cross-sectional view of a known manufacturing process of a CMOS device with a high-k dielectric layer and a metal gate. [0004] First, please refe...

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Problems solved by technology

[0010] However, in the known manufacturing method of CMOS devices, after etching the aluminum oxide layer 114, the lanthanum oxide layer 112, the hafnium oxide layer 110, and the silicon oxide layer 108, polymers or other residues tend to adhere to the device surface. Substances, which will affect the subsequent process, and cause the performance and yield of components to decrease

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