Array substrate, fabricating method for same and liquid crystal display panel
A technology for array substrates and display areas, which is applied in semiconductor/solid-state device manufacturing, instruments, semiconductor devices, etc., can solve the problems of display area 320 size limitation and cannot be further enlarged, and achieve improved utilization, area saving, and crosstalk reduction Effect
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[0062] First embodiment
[0063] reference Figure 5 , Is a schematic top view of the structure of the array substrate according to the first embodiment of the present invention.
[0064] The array substrate is divided into a display area and a frame area surrounding the display area. To simplify the illustration, Figure 5 Only a partial top view of the display area is shown in. The display area includes: a glass substrate; multiple scan lines on the glass substrate: scan line 101, scan line 103, scan line 105, etc., multiple data lines: data line 102, data line 104, data line 106, etc. Each scan line is orthogonal to the data line and insulated from each other. The data line and the scan line are of different layers of metal. The data line is located above the scan line. The two divide the display area into a plurality of pixel areas arranged in an array. Each pixel area includes a thin film transistor 110 and a pixel electrode 120.
[0065] Figure 5 The array structure in has ...
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[0089] Second embodiment
[0090] In the above embodiment, the scan connection line and the scan line are electrically connected through the via hole using other conductive layers, and processes such as alignment, etching, and conductive layer deposition are required to form the via holes located on the scan connection line and the scan line. . As another optional embodiment, the scan connection line and the scan line may also be directly electrically connected without using other conductive layers, thereby simplifying the structure of the array substrate and improving the reliability of the connection.
[0091] Specifically, refer to Picture 20 What is shown is a schematic top view of the structure of the array substrate according to the second embodiment of the present invention. will Figure 19 versus Figure 5 It can be seen by comparison that the difference between this embodiment and the first embodiment is only that the connection structure between the scan connection lin...
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