[0062] First embodiment
[0063] reference Figure 5 , Is a schematic top view of the structure of the array substrate according to the first embodiment of the present invention.
[0064] The array substrate is divided into a display area and a frame area surrounding the display area. To simplify the illustration, Figure 5 Only a partial top view of the display area is shown in. The display area includes: a glass substrate; multiple scan lines on the glass substrate: scan line 101, scan line 103, scan line 105, etc., multiple data lines: data line 102, data line 104, data line 106, etc. Each scan line is orthogonal to the data line and insulated from each other. The data line and the scan line are of different layers of metal. The data line is located above the scan line. The two divide the display area into a plurality of pixel areas arranged in an array. Each pixel area includes a thin film transistor 110 and a pixel electrode 120.
[0065] Figure 5 The array structure in has 2 rows and 2 columns, which is for illustration only. Wherein, the gate of the thin film transistor in each row of pixel area is electrically connected to a scan line, the drain of the thin film transistor 110 in each column of pixel area is electrically connected to a data line, and the source of each thin film transistor passes through the contact hole. 107 is electrically connected to the pixel electrode 120 in the pixel area. The specific connection mode is the same as that of the prior art, as the common knowledge of those skilled in the art, it will not be repeated here.
[0066] In addition, the display area also includes multiple scan connection lines: scan connection line 201, scan connection line 202, scan connection line 203, etc. The scan connection line is arranged parallel to the data line, and the scan line is electrically connected to the external driving chip. Connection (not shown on the figure).
[0067] Specifically, the scan connection line is located below the data line and the scan line (as the bottom metal of the array substrate), and is covered by the data line. E.g Figure 5 Among them, the scan connection line 201 is correspondingly covered by the data line 102, the scan connection line 202 is correspondingly covered by the data line 104, and the scan connection line 203 is correspondingly covered by the data line 106. The advantage of this arrangement is that the scanning connection line does not occupy the area of the pixel area, that is, it avoids affecting the aperture ratio of the display area, and can improve the imaging quality of the array substrate.
[0068] Each scan connection line is connected to a corresponding scan line: for example, the scan connection line 202 and the scan line 101 are connected through the via structure 141, and the scan connection line 203 and the scan line 103 are connected through the via structure 142.
[0069] In order to better explain the above via structure, please refer to Image 6 ,for Figure 5 The cross-sectional structure diagram of the array substrate along the line B-B is shown. The via structure includes: a via 151 connected to the scan connection line 202, a via 152 connected to the scan line 101, and a bridge metal layer 160 covering the above via. Since the scan connection line 202 and the scan line 101 are not located in the same metal layer, the corresponding scan connection line 202 and the scan line 101 can be led out to the same bridge metal layer 160 through the metal-filled vias 151 and 152, and use The bridge metal layer 160 covering the via hole electrically connects the scan connection line 202 and the scan line 101. The bridging metal layer 160 may be the same metal layer as the data line or the pixel electrode, or may be separately fabricated on the top of the array substrate. The via 151 penetrates between the scan connection line 202 and the scan line 101 and the insulating dielectric layer on the surface of the scan line 101, while the via 152 only penetrates the insulating dielectric layer on the surface of the scan line 101. It is necessary to avoid the data lines during production to avoid short circuit between the data lines and the scan lines.
[0070] The scan connection line described in this embodiment is parallel to the data line and located at the bottom layer, so that the scan line is electrically connected to the external driving chip, so that the driving signal of the scan driving chip is transmitted to the scan line, and the pixel area of the corresponding row is selected , Control the turn-on or turn-off of the thin film transistor 110 in each pixel area.
[0071] Then refer to Figure 5 As a complete array substrate, the display area should also include a common electrode 130. The common electrode 130 is located under the pixel electrode 120 and overlaps the pixel electrode 120. An insulating dielectric layer is provided between the two (as shown in the figure). (Not shown), the common electrode 130, the pixel electrode 120, and the insulating medium layer between the two constitute a storage capacitor in the display area.
[0072] As a preferred solution, in this embodiment, the common electrode 130 and the scan line are made of the same layer of metal, which can be patterned and fabricated using the same metal layer, which simplifies the structure of the array substrate and reduces the manufacturing process difficulty of the array substrate.
[0073] As a preferred solution, in this embodiment, the common electrode 130 in each adjacent pixel area is also connected to each other, so that the common electrode 130 is partially located at the bottom of the data line, that is, it crosses the adjacent pixel area and covers the adjacent pixels. The area between districts. The advantage of this arrangement is that since the pixel electrodes located in different pixel areas are independent of each other, the liquid crystal molecules in the areas between adjacent pixel areas in the liquid crystal layer cannot be affected by the electric field and form a disorderly arrangement. In order to avoid this The light leakage of the liquid crystal molecules in the area usually needs to be shielded by a black matrix. The black matrix is located on the color filter substrate. In order to ensure the effect of the alignment deviation of the array substrate and the color filter substrate, the black matrix usually needs to be set wider than the actual shading area. Will reduce the aperture ratio of the liquid crystal display panel. The array substrate provided by this embodiment connects the common electrodes 130 in each adjacent pixel area together, and covers the area between two adjacent pixel areas, reducing the impact of the alignment deviation on the display effect, and can The area of the black matrix is reduced, and the aperture ratio of the liquid crystal display panel is increased.
[0074] It should be further pointed out that since the common electrode 130 and the scan line in this embodiment are the same layer of metal, the scan line has divided the pixel areas of each row, so only the common electrode 130 in the pixel area of the same row can be connected, but not The common electrodes 130 in adjacent pixel regions across rows are connected.
[0075] As a preferred solution, when the common electrode 130 spans adjacent pixel areas and is located at the lower layer of the data line 120, the part of the common electrode 130 can also cover the scan connection line, that is, the layer where the common electrode is located is located at the layer where the data line is located and the scan line is located. Connect the lines between the layers. The advantage of this arrangement is that the common electrode 130 can be driven by DC during the working process of the liquid crystal display panel to avoid interference with the voltage of the scan line of the same layer of metal; and when the common electrode is located on the layer where the data line is located and the scan connection line When located between the layers, the common electrode 130 can also play a shielding role so that there will be no or greatly reduced crosstalk between the scan connection line and the data line or the pixel electrode.
[0076] In order to manufacture the array substrate with the above structure, this embodiment also provides a corresponding manufacturing method. Please refer to Figure 7 to Figure 17 , Is a schematic diagram of the manufacturing method described in this embodiment. It should be pointed out that the following cross-sectional schematic diagrams are not drawn to scale, and focus on showing the main idea of the manufacturing method of the present invention. For clarity, the sizes of layers and regions are enlarged, and the viewing angles of each step are different, and each structure is separately numbered.
[0077] First, refer to Figure 7 , Provide a glass substrate 400, the glass substrate 400 is divided into a display area and a frame area, the frame area surrounds the display area. To simplify the description, the following figure only shows a schematic cross-sectional view of the display area.
[0078] reference Figure 8 As shown, a first metal layer 500 is formed on the surface of the glass substrate 400, and the first metal layer may be physical vapor deposition (PVD) or chemical vapor deposition (CVD) or metal organic compound chemical vapor deposition (MOCVD) And other methods to form.
[0079] reference Picture 9 As shown, a first mask is used to pattern the first metal layer 500 using a photolithography process to form a scan connection line 501. The scan connection line 501 will be used for electrical connection with an external driving chip. The connecting lines 501 are parallel to each other.
[0080] reference Picture 10 As shown, a first insulating dielectric layer 601 is formed on the surface of the scan connection line 501 and the glass substrate 400. The first insulating dielectric layer 601 can be formed by chemical vapor deposition, and the material can be conventional insulating materials such as silicon nitride, silicon oxide, or silicon oxynitride.
[0081] reference Picture 11 As shown, a second metal layer 700 is formed on the surface of the first insulating dielectric layer 601, and the second metal layer 700 can also be formed by processes such as chemical vapor deposition, physical vapor deposition, or the like.
[0082] reference Picture 12 In order to etch the top view of the substrate of the second metal layer, the second metal layer 700 is patterned by using a second mask and a photolithography process to form scan lines 701 and common electrodes 702. Between the scan lines 701 They are parallel to each other but perpendicular to the scanning connection line 501. Generally, when the second metal layer 700 is patterned, the gate 703 of the thin film transistor can also be formed at the same time. The pixel regions arranged in an array in the display area can be defined in advance, the gate 703 of the thin film transistor is fabricated in each pixel region, and the gate 703 in the pixel region of the same line is electrically connected to a corresponding scan line 701. In addition, the common electrodes 702 in the pixel areas of the same row are connected to cover the area between adjacent pixel areas. In addition, when defining the pixel area, the scan connection line 501 should also be located in the area between adjacent pixel areas, so that the common electrode 702 can cover the scan connection line 501.
[0083] reference Figure 13 Shown (section view, section line is Picture 12 D-D line in), in Picture 12 On the basis of the structure shown, the second insulating dielectric layer 602, the amorphous silicon layer 603, and the doped amorphous silicon layer 604 are continuously formed, and then the amorphous silicon layer 603 is etched using a third mask and photolithography process. The doped amorphous silicon layer 604 forms the active layer of the desired thin film transistor. The second insulating dielectric layer 602 can be used as a gate dielectric layer of a thin film transistor. The amorphous silicon layer 603 is used to form a conductive channel of the thin film transistor, and the doped amorphous silicon layer 604 is used to form an ohmic contact with the source and drain electrodes formed subsequently.
[0084] reference Figure 14 , A third metal layer 800 is formed, and the third metal layer 800 is used to form the source and drain electrodes of the data line and the thin film transistor.
[0085] reference Figure 15 , The third metal layer 800 is etched using a fourth mask and a photolithography process to form the data line 801 and the source electrode 802 and the drain electrode 803 of the thin film transistor, and the data line 801 covers each corresponding scan connection line below it 501, also can refer to Figure 16 for Figure 15 DD cross-sectional view, the third metal layer 800 will be slightly over-etched when the third metal layer 800 is etched, and the doped amorphous silicon layer 604 will be etched off to expose the amorphous silicon layer 603 underneath, so that the source 802 of the thin film transistor is The drain 803 is connected to the corresponding silicon island and insulated from each other. Each data line 801 is connected to the source 802 of the thin film transistor in the pixel area of the same column. The plurality of data lines 801 and the plurality of scan lines 701 are perpendicular to each other and form orthogonal, that is, each pixel area can be divided. Further, the data line 801 in this embodiment also covers the scan connection line 501, so that in the light transmission direction, the data line 801, the common electrode 702, and the scan connection line 501 overlap.
[0086] reference Figure 17 , A third insulating dielectric layer 900 is formed to cover the back substrate 400 formed in the above process, and the third insulating dielectric layer 900, the second insulating dielectric layer 602, and the first insulating dielectric layer are etched using a fifth mask and a photolithography process 601, forming a via 901 on the drain 803 of the thin film transistor to expose the drain 803 through the third insulating dielectric layer 900, and forming a via 605 on the scan connection line 501 to allow the scan connection line 501 to pass through the The three insulating dielectric layer 900, the second insulating dielectric layer 602, and the first insulating dielectric layer 601 are exposed. Also please refer to Figure 18 , Figure 18 for Figure 17 In the top view, the via 606 on the scan line 701 is also formed to expose the scan line 701 through the third insulating dielectric layer 900, the second insulating dielectric layer 602, and the first insulating dielectric layer 601.
[0087] reference Figure 19 As shown, a pixel electrode layer is formed, and the pixel electrode layer is etched using a sixth mask and a photolithography process to form a pixel electrode 902 in each pixel area. The pixel electrode 902 is connected to the thin film in the same pixel area through the contact hole 901. The source of the transistor is connected and has an overlap with the common electrode 702. In this way, the common electrode 702, the protective insulating layer, and the pixel electrode 902 constitute a storage capacitor in the display area of the array substrate. When the pixel electrode layer is formed, the pixel electrode layer is also deposited in the vias 605 and 606, and the scan connection line 501 and the scan line 701 are electrically connected through the pixel electrode layer; when the pixel electrode layer is etched, a connection scan connection is formed The connecting portion 903 of the line 501 and the scanning line 701. It should be noted that the material of the pixel electrode 902 in this embodiment is indium tin oxide (ITO).
[0088] After the above-mentioned manufacturing process, the array substrate described in this embodiment is formed.
