Method for processing porous low-K-value dielectric by plasmas
A plasma, K value technology, applied in semiconductor/solid state device manufacturing, electrical components, circuits, etc., to achieve the effect of reducing diffusion, inhibiting the increase of K value, and inhibiting the reduction of device performance
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Embodiment 1
[0021] After depositing a porous low-K dielectric film 11 on a substrate 1 through a film deposition process, it is placed between the upper electrode 12 and the lower electrode 13 of the RIE machine; wherein, the lower plate 13 is connected to a radio frequency source 14 , the upper plate 12 is grounded and located directly above the lower plate 13 .
[0022] Then, turn on the radio frequency source 14 of the RIE machine and pass NH between the upper electrode 12 and the lower electrode 13 at the same time 3 or CH 4 or NH 3 、CH 4 As the main processing gas 16, the processing gas 16 is excited into a plasma 15 with a high polymer density, and the plasma 15 reacts with the porous low-K dielectric film 11 and forms a passivation layer 17 on its surface to treat the porous low-K dielectric film 11. Carry out sealing; Wherein, while passing through processing gas 16, selectively add appropriate amount of H 2 Or Ar, etc. are used to adjust the uniformity of the reaction and the...
Embodiment 2
[0027] After etching the second dielectric layer 35 on a pair of damascene mechanisms 3, it is placed between the upper electrode 22 and the lower electrode 23 of the RIE machine; wherein, the lower plate 23 is connected to the radio frequency source 24, and the upper plate 22 grounded and located directly above the lower plate 23 .
[0028] Further, the double damascene mechanism 3 includes a first dielectric layer 31 disposed underneath and a Ta or TaN metal barrier layer 32 embedded therein, a metal copper layer 33 covering the Ta or TaN metal barrier layer 32, and an SiCO or SiCN etch barrier layer 34 Covering the first dielectric layer 31, the Ta or TaN metal barrier layer 32 and the metal copper layer 33, the second dielectric layer 35 covers the SiCO or SiCN etching barrier layer 34, and the metal via 36 penetrates the second dielectric layer 35 and the SiCO or SiCN etching barrier layer. The etch stop layer 34 stops on the metal copper layer 33; wherein, the first diel...
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