Method for avoiding contact hole blockage caused by dual etching barrier layers

Abstract

The invention discloses a method for avoiding contact hole blockage caused by dual etching barrier layers, wherein the method mainly comprises the steps of: respectively growing a silicon oxide layer used as a protective layer of subsequent wet process etching on the upper surfaces of a first layer of pressure stress etching barrier layer silicon nitride and a second layer of pressure stress etching barrier layer; and etching an upper layer of pressure stress etching barrier layer silicon nitride of an overlapping part of a P-type trap and an N-type trap by adopting a lateral wet process etching process. By using the method for avoiding the contact hole blockage caused by the dual etching barrier layers, the upper layer of pressure stress etching barrier layer silicon nitride of the overlapping layer of the P-type trap and the N-type trap is effectively etched, so that the residual pressure stress etching barrier layer silicon nitride does not influence the increase of hole mobility of a P-type channel metal oxide semiconductor, thus the problem of contact hole etching blockage in a subsequence process is avoided.

Description

technical field [0001] The invention relates to a process integration method, in particular to a method for avoiding contact hole blockage caused by double etching barrier layers. Background technique [0002] In the semiconductor manufacturing process, as the feature size continues to shrink into the nanometer era, it is difficult to simply improve the performance of complementary metal oxide semiconductor devices due to physical limitations such as the derived short channel effect and the thickness of traditional dielectrics approaching the limit. Follow the traditional proportional reduction method. [0003] Strain technology changes the energy band structure of silicon in the channel region by introducing appropriate strain, thereby increasing the mobility of carriers, so that the performance of the device can continue to be improved when it is scaled down, so it has been widely developed and applied. There are a variety of techniques to create strain in the channel reg...

AI Technical Summary

Problems solved by technology

The N-type well and the P-type well used to solve the problem of complementary metal oxide semiconductors in the prior art have an overlapping area, and the etching barrier layer nitride of the N-type well and the P-type well in the overlapping area forms two overlapping layers, and the opposite The contact hole in the overlapping area of ​​the N-type well and the P-type well poses great difficulties to the subsequent contact hole etching, and easily leads to the problem of contact hole failure.

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