Parallel design circuit for realizing bit stuffing

Abstract

The invention provides a parallel design circuit for realizing bit stuffing, which comprises a delay unit, a judgment object reorganization unit, a reference object reorganization unit, a judging unit, a stuffing unit and an accumulating unit, wherein the delay unit delays input data; the judgment object reorganization unit reorganizes the data subject to clock period delay and outputs an judgment object; the reference object reorganization unit reorganizes the data output by the circuit and outputs a reference object; the judging unit judges which bits of the judgment object output by the judgment object reorganization unit need to be stuffed according to the reference object and outputs the judgment result to the stuffing unit; the stuffing unit performs bit stuffing operation, outputs the number of the currently stuffed bits to the accumulating unit and outputs the result after bit stuffing as the operating result of the entire circuit; and the accumulating unit accumulates the number of the stuffed bits and outputs the result to the input end of the judgment object reorganization unit. Compared with the design and the bit stuffing operation of the traditional circuit, the parallel design circuit has the advantage that power consumption in the circuit can be greatly reduced.

Description

technical field [0001] The invention relates to a USB interface design circuit, in particular to a parallel design circuit for realizing bit filling. Background technique [0002] With the rapid development of microelectronic technology, devices with USB2.0 interfaces have been widely used in electronic products in daily life. USB is a serial bus in which data is transmitted bit by bit sequentially. The data transmission in the USB system adopts the reverse non-return to zero (NRZI, Non Return to Zero Invert) encoding method. This encoding method can not only ensure the integrity of the data transmission, but also does not require an independent clock signal to be sent together with the data. When a 0 signal is encountered, the NRZI encoded data stream jumps; when a 1 signal is encountered, it remains unchanged. Transitions in the data stream allow the decoder to synchronize with the received data, eliminating the need for a separate clock signal. But a long string of con...

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Problems solved by technology

But a long string of consecutive 1s will cause no level transitions, causing the receiver to eventually lose the sync signal

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