Contact hole and manufacturing method thereof as well as semiconductor device
A manufacturing method and semiconductor technology, applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve problems such as contact hole leakage, affecting insulation, and unfavorable performance of semiconductor devices
- Summary
- Abstract
- Description
- Claims
- Application Information
AI Technical Summary
Problems solved by technology
Method used
Image
Examples
Embodiment 1
[0041] This embodiment one takes the commonly used MOS transistor structure as an example, the following combination figure 2 The flow chart shown in the figure introduces in detail the method for forming the contact hole provided by the first embodiment, so as to solve the above-mentioned problems.
[0042] Such as image 3As shown, first, step S11 is performed to provide a semiconductor substrate 10, and the provided semiconductor substrate 10 is formed with a MOS transistor structure, specifically, the MOS structure includes a defined source region 11, a drain region 12, and a source region 11 A gate dielectric layer 13 and a gate 14 are sequentially formed on the channel region (not shown) between the drain region 12 .
[0043] In the first embodiment, the semiconductor substrate 10 is silicon.
[0044] Such as Figure 4 As shown, next, step S12 is performed to deposit dielectric layers 16 and 15 on the source region 11 , the drain region 12 and the gate 14 respectivel...
Embodiment 2
[0062] In recent years, in order to reduce the on-resistance of the power MOSFET device, a trench semiconductor device (Trench MOSFET) has been proposed in the industry. Taking the trench MOS transistor as an example, the method for forming the contact hole provided in the second embodiment will be described below.
[0063] Such as Figure 8 As shown, first, step S21 is performed to provide a semiconductor substrate, and the provided semiconductor substrate is formed with a trench type MOS structure, specifically, the trench type MOS structure includes an N-type semiconductor silicon substrate 30, and the N-type A homogeneous epitaxial layer 31 (i.e. also N-type) of the substrate 30, a trench is formed in the epitaxial layer 31, and two source regions 32 are defined on both sides of the trench; the trench is filled with an insulating layer 33 and polysilicon in sequence 34 , the insulating layer 33 is a gate insulating layer, the polysilicon 34 is a gate, and the drain of the...
PUM
Login to View More Abstract
Description
Claims
Application Information
Login to View More 