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Contact hole and manufacturing method thereof as well as semiconductor device

A manufacturing method and semiconductor technology, applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve problems such as contact hole leakage, affecting insulation, and unfavorable performance of semiconductor devices

Active Publication Date: 2012-07-11
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] However, the inventors found that when BPSG is selected as the dielectric layer, when the semiconductor substrate with the contact hole is annealed to form titanium silicide, the dielectric layer BPSG has a stress difference with the conductive material, resulting in the dielectric There are often some cracks 1 (crack) in the layer, and the SEM test results are as follows figure 1 As shown, the crack 1 will affect the insulation of the BPSG dielectric layer, resulting in leakage of the contact hole, which is not conducive to the performance of the semiconductor device

Method used

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  • Contact hole and manufacturing method thereof as well as semiconductor device
  • Contact hole and manufacturing method thereof as well as semiconductor device
  • Contact hole and manufacturing method thereof as well as semiconductor device

Examples

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Embodiment 1

[0041] This embodiment one takes the commonly used MOS transistor structure as an example, the following combination figure 2 The flow chart shown in the figure introduces in detail the method for forming the contact hole provided by the first embodiment, so as to solve the above-mentioned problems.

[0042] Such as image 3As shown, first, step S11 is performed to provide a semiconductor substrate 10, and the provided semiconductor substrate 10 is formed with a MOS transistor structure, specifically, the MOS structure includes a defined source region 11, a drain region 12, and a source region 11 A gate dielectric layer 13 and a gate 14 are sequentially formed on the channel region (not shown) between the drain region 12 .

[0043] In the first embodiment, the semiconductor substrate 10 is silicon.

[0044] Such as Figure 4 As shown, next, step S12 is performed to deposit dielectric layers 16 and 15 on the source region 11 , the drain region 12 and the gate 14 respectivel...

Embodiment 2

[0062] In recent years, in order to reduce the on-resistance of the power MOSFET device, a trench semiconductor device (Trench MOSFET) has been proposed in the industry. Taking the trench MOS transistor as an example, the method for forming the contact hole provided in the second embodiment will be described below.

[0063] Such as Figure 8 As shown, first, step S21 is performed to provide a semiconductor substrate, and the provided semiconductor substrate is formed with a trench type MOS structure, specifically, the trench type MOS structure includes an N-type semiconductor silicon substrate 30, and the N-type A homogeneous epitaxial layer 31 (i.e. also N-type) of the substrate 30, a trench is formed in the epitaxial layer 31, and two source regions 32 are defined on both sides of the trench; the trench is filled with an insulating layer 33 and polysilicon in sequence 34 , the insulating layer 33 is a gate insulating layer, the polysilicon 34 is a gate, and the drain of the...

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PUM

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Abstract

The invention provides a manufacturing method of a contact hole. The method comprises the following steps of: providing a semiconductor substrate; depositing BPSG (Boro-Phospho-Silicate-Glass) medium layers on a source region, a drain region and a gate of the semiconductor substrate; forming a first channel, a second channel and a third channel, which are respectively exposed out of the surfaces of the source region, the drain region and the gate, within the medium layers; forming a Ti metal layer and a TiN diffusion impervious layer in the first to third channels in sequence, wherein the TiN diffusion impervious layer is generated through carrying out physical vapor deposition on a N2 and Ar mixed gas and a Ti target; rapidly carrying out heat annealing on the semiconductor substrate so as to form metal silicide of Ti; and forming a metal layer, which is filled in each channel, on the TiN diffusion impervious layer. In addition, the invention also provides a contact hole formed by using the method as well as a semiconductor device including the contact hole. By adopting the technical scheme provided by the invention, the BPSG medium layers are prevented from being easily cracked in the annealing process.

Description

technical field [0001] The invention relates to a contact hole, a method for making the contact hole, and a semiconductor device including the contact hole. Background technique [0002] With the development of integrated circuits to ultra-large-scale integrated circuits, the circuit density inside integrated circuits is increasing, and the number of components contained is also increasing. This development makes the surface of the wafer unable to provide enough area to manufacture the required interconnecting wires. [0003] In order to meet the requirements of interconnection lines after shrinking components, the design of two or more layers of multilayer metal interconnection lines has become a common method in VLSI technology. At present, the conduction between the metal layer and the substrate is realized through a contact hole structure. [0004] The formation purpose of the contact hole structure is to form a metal contact in the active area. The metal contact can ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/768
Inventor 汪洋
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP