Array substrate, manufacturing method thereof and display device
A technology for array substrates and manufacturing methods, applied in the fields of array substrates and their manufacturing methods, and display devices, capable of solving problems such as changes in material properties, increasing equipment investment, and reducing thin-film transistors, so as to improve stability, reduce the number of times, and reduce costs Effect
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Embodiment 1
[0063] The specific description of the fabrication process of the array substrate in this embodiment is as follows:
[0064] First, an oxide semiconductor layer pattern 2 is formed on a glass substrate 1 . Such as figure 1 As shown, it is a cross-sectional view of an oxide semiconductor layer pattern 2 formed on a glass substrate. The formation process is: depositing an oxide semiconductor thin film on a glass substrate 1. The material of the oxide semiconductor is IGZO or ZnO, and its thickness is between Coating photoresist on the oxide semiconductor film, using a mask to expose and develop the photoresist, retaining the photoresist in the pattern area 100 of the semiconductor layer; etching away the exposed oxide semiconductor film, and removing the remaining photoresist to form the oxide semiconductor layer pattern 2.
[0065] Next, a gate insulating layer pattern 4 and a gate pattern 5 are formed on the oxide semiconductor layer pattern 2 . Such as figure 2 As shown...
Embodiment 2
[0073] Another manufacturing method of the above-mentioned array substrate in this embodiment is as follows:
[0074] Such as Figure 9 As shown, an oxide semiconductor film, an insulating film and a gate metal film are sequentially deposited on a glass substrate 1 . The material of the oxide semiconductor thin film is IGZO or ZnO, and its thickness is between The material of the insulating film can be silicon nitride, silicon oxide, or aluminum oxide, etc. The material of the gate metal can be metals such as aluminum, copper, or alloys of metals such as aluminum and neodymium. The thickness of the insulating film is
[0075] Such as Figure 10 As shown, the photoresist 12 is coated on the gate metal film, and the photoresist 12 is exposed and developed through a double-tone mask (half-tone mask or gray-tone mask), and the pattern area of the metal diffusion layer is reserved. 104, the photoresist 12 of the gate insulating layer, the gate and the gate line pattern area...
Embodiment 3
[0085] This embodiment provides an array substrate, which can be prepared by the method of the above-mentioned embodiment 1 or embodiment 2, and its structure is as follows Figure 8 As shown, it includes: a semiconductor layer 2 formed on a glass substrate 1 , a gate insulating layer 4 , a gate 5 , a barrier layer 6 , a passivation layer 7 , source and drain electrodes 8 and a pixel electrode 9 . A gate insulating layer 4 and a gate 5 are sequentially formed on the semiconductor layer 2 . The gate insulating layer 4 and the gate 5 are located in the middle of the semiconductor layer 2 and have the same shape and size. A metal diffusion layer 2 is also formed on the region of the semiconductor layer 2 not covered by the gate insulating layer 4 . Its formation process is as described in Example 1 or Example 2. A metal film is deposited on the semiconductor layer 2, preferably Al (because Al has better diffusivity and can form a dense protective layer after oxidation). Al is o...
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