Through-silicon-vias structure and formation method thereof

Abstract

The invention relates to a through-silicon-vias structure and a formation method thereof. The formation method includes that a semiconductor substrate is provided, the semiconductor substrate includes an upper surface and a lower surface which are opposite to each other, the upper surface of the semiconductor substrate is subjected to an etching to form an opening, a conducting material is filled in the opening to form first connecting pegs, the lower surface of the semiconductor substrate is subjected to the etching to form a groove, the first connecting pegs are exposed at the bottom of the groove, a conducting material which is capable of being etched is filled in the groove, the conducting material which is capable of being etched is subjected to the etching to form second connecting pegs, each of the second connecting pegs is vertically connected with each of the first connecting pegs, and dielectric layers are filled gaps between the second connecting pegs and the semiconductor substrate and gaps between adjacent second connecting pegs. The through-silicon-vias structure and the formation method thereof have the advantages that the reliability of the through-silicon-vias structure is improved, and the cavity defect is prevented.

Description

Technical field [0001] The present invention relates to the field of semiconductor technology, in particular to a through-silicon via structure and a method for forming the same. Background technique [0002] 3D packaging stacks two or more integrated circuits vertically in the same chip, which can reduce the space occupied. The substrates commonly used in 3D packaging for carrying integrated circuits often have a through-silicon via structure (TSV, Through-Silicon). -Vias). By using the through silicon via structure to replace the traditional edge wiring for 3D packaging, more logic functions can be integrated in a small device footprint. In addition, the adoption of the through silicon via structure can effectively shorten the critical path, reduce the delay, and increase the device speed. [0003] The through silicon via structure is mainly to form a through hole on a semiconductor substrate, and fill it to form a nail, and then connect the nail to the interconnect structure o...

AI Technical Summary

Problems solved by technology

[0013] The problem solved by the present invention is that in the prior art, as the aspect ratio increases, the reliability of the through-silicon via structure based on the copper interconnection process decreases.

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