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Interconnection structure and forming method thereof

An interconnection structure and interconnection layer technology, applied in electrical components, electrical solid devices, circuits, etc., can solve the problems of reducing the effective utilization of circuit design area, occupying the effective area of ​​the circuit, etc., to reduce the degradation phenomenon of the gate oxide layer , the effect of reducing the degradation phenomenon and reducing the area

Active Publication Date: 2012-11-21
SEMICON MFG INT (SHANGHAI) CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, such a method needs to be completed in the front-end process of semiconductor manufacturing. If it is necessary to effectively avoid plasma damage, a large number of such diodes are required, occupying a lot of effective area of ​​the circuit, and reducing the effective utilization of the circuit design area.

Method used

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  • Interconnection structure and forming method thereof
  • Interconnection structure and forming method thereof
  • Interconnection structure and forming method thereof

Examples

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Effect test

Embodiment 1

[0052] Embodiment 1: Reference image 3 and Figure 4 What is shown is a schematic cross-sectional structure diagram of the first embodiment of the method for forming an interconnection structure according to the present invention.

[0053] Specifically, such as image 3 As shown, firstly, a semiconductor substrate 20 is provided, on which there are semiconductor devices. To simplify the diagram, only a blank semiconductor substrate is shown here.

[0054] Then, an interconnection structure is formed on the semiconductor substrate 20 , the interconnection structure includes a metal layer 215 , and the metal layer 215 is located in the insulating dielectric layer 216 and is flush with the surface of the insulating dielectric layer 216 . Optionally, the material of the metal layer 215 is copper, and the material of the insulating dielectric layer 216 is silicon oxide. The specific process for forming the insulating dielectric layer 216 and the metal layer 215 is the prior art...

Embodiment 2

[0063] Embodiment two: reference Figure 5 and Image 6 What is shown is a schematic cross-sectional structure diagram of the second embodiment of the method for forming an interconnection structure according to the present invention.

[0064] Specifically, such as Figure 5 As shown, firstly, a semiconductor substrate 20 is provided, on which there are semiconductor devices. To simplify the diagram, only a blank semiconductor substrate is shown here.

[0065] Then, an interconnection structure is formed on the semiconductor substrate 20 , the interconnection structure includes metal layers 215 , 219 , and the metal layers 215 , 219 are located in the insulating dielectric layer 216 and flush with the surface of the insulating dielectric layer 216 . Optionally, the material of the metal layers 215 and 219 is copper, and the material of the insulating dielectric layer 216 is silicon oxide. The specific process method for forming the insulating dielectric layer 216 and the me...

Embodiment 3

[0072] Embodiment three: reference Figure 7 A schematic diagram of a first embodiment of an interconnection structure of the present invention including pads is shown. This embodiment is a schematic diagram of forming an interconnection structure including pads by performing a back-end process on the basis of the interconnection structure formed in the first embodiment above.

[0073] Specifically, such as Figure 7 As shown, first, the first dielectric barrier layer 22 is formed on the interlayer dielectric layer 214 and the metal wiring layer 212, wherein the material of the first dielectric barrier layer 22 is silicon nitride or silicon carbide or silicon carbonitride . The function of the first dielectric barrier layer 22 is to prevent the subsequent passivation layer 23 from oxidizing the metal wiring layer 212 .

[0074] Then, a passivation layer 23 is formed on the first dielectric barrier layer 22, wherein the material of the passivation layer 23 is silicon oxide. ...

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PUM

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Abstract

The invention provides an interconnection structure and a forming method of the interconnection structure. The interconnection structure comprises a semiconductor substrate, a metal layer on the semiconductor substrate, an interlayer medium layer on the metal layer, and a discrete metal wiring layer formed inside the interlayer medium layer; the metal wiring layer is a top metal layer with an interconnection structure; the metal wiring layer is divided into a brim area and an interior area, and the brim area and the interior area are isolated through the interlayer medium layer. According to the technical scheme, the area range of electric connection between the metal wiring layer and below adjacent metal layer is reduced by connecting the brim area of the metal wiring layer and below adjacent metal layer, so that the degeneracy phenomenon of a gate oxidation layer due to the fact that plasma generated when a metal welding plate layer in a semiconductor interconnection structure is fabricated penetrates into the substrate can be reduced.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to an interconnection structure and a forming method thereof. Background technique [0002] In the semiconductor integrated circuit manufacturing process, in order to increase the device density on a single integrated circuit chip, it is necessary to reduce the process size of the semiconductor device. However, as the density of devices on a chip continues to increase, it is necessary to increase the number of interconnection structure metal layers on the chip while reducing the size of the device to effectively realize the conduction of various semiconductor devices on the chip. Existing semiconductor interconnect structures such as figure 1 shown. Specifically, the interconnect structure includes: a semiconductor substrate 10, on which semiconductor devices or interconnect lines are formed; on the semiconductor substrate 10, a metal layer 115 is formed, and t...

Claims

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Application Information

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IPC IPC(8): H01L23/485H01L23/488H01L21/786
Inventor 卑多慧
Owner SEMICON MFG INT (SHANGHAI) CORP
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