Formation method of deep groove super positive-negative (PN) junction

Abstract

The invention relates to a formation method of a deep groove super PN junction. The method comprises the steps of depositing an epitaxial layer on a substrate; forming a first dielectric layer and a second dielectric layer on the epitaxial layer sequentially; forming a deep groove on the epitaxial layer; filling the deep groove with epitaxial materials till the specified height of the second dielectric layer is exceeded; etching epitaxial materials, the first dielectric layer and the second dielectric layer till the interface positions of the first dielectric layer and epitaxial materials with etching gases; and removing the first dielectric layer and the second dielectric layer to achieve planarization of epitaxial materials. By the aid of the formation method, planarization of silicon can be achieved by using the method which is compatible with existing processes, the formation method has the advantages of being simple in process, high in efficiency and low in process cost, and the problem that parameters of silicon (Si) devices are not stable due to chemical-mechanical polishing (CMP) can be effectively solved.

Description

technical field [0001] The present invention relates to semiconductor manufacturing technology, in particular to a deep trench super PN junction (Super Junction) manufacturing technology. Background technique [0002] In the field of semiconductors, the super PN junction (Super Junction) technology used to improve the performance of power MOS plays a very significant role in the high voltage field. [0003] The traditional manufacturing process of super PN junction mainly adopts the methods of deep trench etching, epitaxial filling, and silicon CMP planarization. Specifically, the method for forming a super PN junction in the traditional technology includes the following steps: [0004] Step 1: Deposit a single thick epitaxial layer (N-type) on the N+ substrate silicon wafer; [0005] Step 2: Form a deep trench in the epitaxial layer, specifically, first grow a thermal oxide layer, then deposit a silicon nitride layer, and then deposit a plasma-enhanced oxide layer, etch t...

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Problems solved by technology

[0008] However, in the technology using CMP, because the CMP equipment of the general production line is used in the back channel, it cannot be mixed with the equipment for processing the super PN junction. Therefore, the method of manufacturing the super PN junction using CMP planarization must use special CMP equipment As a result, the process control is difficult and the cost is high

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