How to make a metal gate

Abstract

The invention discloses a method for manufacturing a metal gate. The method first provides a substrate. At least one semiconductor element is formed on the substrate, and the semiconductor element has a conductive type. Next, a gate trench is formed in the semiconductor element. After the gate trench is formed, a work function metal layer is formed in the gate trench. The work function metal layer has the conductivity type and a predetermined conductivity type corresponding to the conductivity type. Set up the work function. Finally, an ion implantation process is performed to adjust the preset work function to a target work function, and the target work function corresponds to the conductivity type.

Description

technical field [0001] The invention relates to a metal grid and its manufacturing method, especially to a metal grid using a gate last process and its manufacturing method. Background technique [0002] As the size of semiconductor devices continues to shrink, the traditional method of reducing the gate dielectric layer, such as reducing the thickness of the silicon dioxide layer, to achieve the purpose of optimization, is facing problems caused by the tunneling effect of electrons. Physical limitation of excessive leakage current. In order to effectively extend the generation evolution of logic elements, high dielectric constant (high dielectric constant, hereinafter referred to as high-k) materials can effectively reduce the physical limit thickness, and under the same equivalent oxide thickness (equivalent oxide thickness, EOT) , effectively reducing the leakage current and achieving equivalent capacitance to control the channel switch, etc., and is used to replace the ...

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Problems solved by technology

[0003] However, polysilicon, the traditional gate material, faces problems such as boron penetration (boron penetration), which leads to lower device performance; and the polysilicon gate encounters the unavoidable depletion effect, making the equivalent gate dielectric layer Thickness increases, gate capacitance decreases, and then leads to the decline of device driving ability and other difficulties

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