Metal oxide semiconductor (MOS) transistor and forming method thereof

Abstract

The invention discloses a forming method of a metal oxide semiconductor (MOS) transistor. The method includes that a semiconductor substrate is provided, a dielectric layer is formed on the surface of the semiconductor substrate, the dielectric layer is provided with an opening which exposes the semiconductor substrate, a groove is formed in the semiconductor substrate along the opening, a semiconductor filled layer is formed in the groove, and a gate structure filling the opening is formed. A forming method for a complementary metal oxide semiconductor (CMOS) transistor, which utilizes the forming method for the MOS transistor, the corresponding MOS transistor and the corresponding CMOS transistor are further provided. Thereby, the threshold voltage of a p-channel metal oxide semiconductor (PMOS) transistor can be reduced.

Description

technical field [0001] The invention relates to the semiconductor field, in particular to a MOS transistor and a forming method thereof. Background technique [0002] With the continuous development of integrated circuit manufacturing technology, the feature size of MOS transistors is getting smaller and smaller. As the feature size of MOS transistors keeps shrinking, in order to reduce the parasitic capacitance of the gate of MOS transistors and increase the device speed, the gate stack structure of high-K gate dielectric layer and metal gate is introduced into MOS transistors. [0003] In order to avoid the influence of the metal material of the metal gate on other structures of the transistor, the gate stack structure of the metal gate and the high-K gate dielectric layer is usually fabricated by a gate replacement (replacement gate) process. In this process, before the implantation of the source and drain regions, a sacrificial gate made of polysilicon is first formed a...

AI Technical Summary

Problems solved by technology

[0011] However, the threshold voltage of the CMOS transistor formed by the above method is relatively large. One way to reduce the threshold voltage is to form a functional metal layer between the gate dielectric layer and the gate electrode layer, but the CMOS transistor formed by this method The threshold voltage is still not small enough

Images