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Multi-chip flip-chip etching first packaging structure without base island and its manufacturing method

A technology of packaging structure and manufacturing method, which is used in semiconductor/solid-state device manufacturing, electrical components, and electrical solid-state devices, etc., and can solve problems such as large differences in material properties, stress deformation, and reliability levels affecting reliability, safety capabilities, etc. Achieve the effect of not easy stress deformation, reduce environmental pollution, and improve safety

Active Publication Date: 2014-10-29
JCET GROUP CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0019]3. Glass fiber itself is a kind of foaming material, so it is easy to absorb moisture and moisture due to the storage time and environment, which directly affects the reliability and safety ability or is the level of reliability;
[0020] 4. The surface of the glass fiber is covered with a copper foil metal layer thickness of about 50-100 μm, and the etching distance between the metal layer line and the line can only achieve an etching gap of 50-100 μm due to the characteristics of the etching factor (see Figure 36 , the best production capacity is that the etching gap is approximately equal to the thickness of the etched object), so it is impossible to truly design and manufacture high-density circuits;
[0022]6. Also because the entire substrate material is made of glass fiber, the thickness of the glass fiber layer is obviously increased by 100~150μm, and it cannot be really ultra-thin encapsulation;
[0023]7. Due to the large difference in material characteristics (expansion coefficient) of the traditional glass fiber plus copper foil technology, it is easy to cause stress deformation in the harsh environment process, directly Affects the accuracy of component loading and the adhesion and reliability of components and substrates

Method used

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  • Multi-chip flip-chip etching first packaging structure without base island and its manufacturing method
  • Multi-chip flip-chip etching first packaging structure without base island and its manufacturing method
  • Multi-chip flip-chip etching first packaging structure without base island and its manufacturing method

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0101] Example 1: No Base Island Single Turn Pin

[0102] Referring to FIG. 20(A) and FIG. 20(B), FIG. 20(A) is a schematic structural diagram of Embodiment 1 of the multi-chip flip-chip packaging structure of the present invention, which is etched first and packaged without a base island. FIG. 20(B) is a top view of FIG. 20(A). It can be seen from Fig. 20(A) and Fig. 20(B) that the multi-chip flip-chip package structure of the present invention is etched first and then packaged without a base island. It includes pins 1 and chips 2. There are multiple chips 2, so The plurality of chips 2 are flip-chip on the front of the pin 1, and an underfill glue 13 is provided between the bottom of the chip 2 and the front of the pin 1, and the area around the pin 1, between the pin 1 and the pin 1 The area of ​​the upper part of the pin 1 and the lower part of the pin 1, and the outside of the chip 2 are all encapsulated with a plastic compound 3, and the surface of the plastic compound ...

Embodiment 2

[0145] Embodiment 2, no base island single-turn pin passive device

[0146] Referring to FIG. 21(A) and FIG. 21(B), FIG. 21(A) is a schematic structural diagram of Embodiment 2 of the multi-chip flip-chip, etch-first, and package-without-base-island packaging structure of the present invention. FIG. 21(B) is a top view of FIG. 21(A). It can be seen from Fig. 21(A) and Fig. 21(B) that the only difference between Embodiment 2 and Embodiment 1 is that the passive connection between pin 1 and pin 1 is bridged by a conductive bonding material. The device 7, the passive device 7 may be connected between the front of the pin 1 and the front of the pin 1, or may be connected between the back of the pin 1 and the back of the pin 1.

Embodiment 3

[0147] Example 3: Multiturn pins without base island

[0148] Referring to FIG. 22(A) and FIG. 22(B), FIG. 22(A) is a schematic structural diagram of Embodiment 3 of the multi-chip flip-chip etching first packaging structure without base island of the present invention. Fig. 22(B) is a top view of Fig. 22(A). It can be seen from FIG. 22(A) and FIG. 22(B) that the only difference between embodiment 3 and embodiment 1 is that the pin 1 has multiple turns.

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Abstract

The invention relates to a multi-chip flip, packaging-after-etching and non-pad packaging structure and a manufacturing method thereof. The structure comprises pins (1) and a plurality of chips (2). The plurality of the chips (2) are arranged on the right sides of the pins (1) in an inverted mode; bottom filling glue (13) is arranged between the bottoms of the chips (2) and the right sides of the pins (1); molding compounds (3) are packaged in areas on the peripheries of the pins (1), among the pins (1), on the upper portions and the lower portions of the pins (1) and outside the chips (2); holes (4) are opened on the surfaces of the molding compounds (3) on the lower portions of the pins (1), and communicated with the reverse sides of the pins (1); and metal balls (6) are arranged in the holes (4) and contacted with the reverse sides of the pins (1). The multi-chip flip, packaging-after-etching and non-pad packaging structure and the manufacturing method thereof have the advantages of reducing manufacturing costs, improving safety and reliability of packaging bodies, and being capable of designing and manufacturing high-density lines.

Description

technical field [0001] The invention relates to a multi-chip flip-chip, etch first and then package baseless island package structure and a manufacturing method thereof, belonging to the technical field of semiconductor packaging. Background technique [0002] The manufacturing process flow of the traditional high-density substrate package structure is as follows: [0003] Step 1, see Figure 24 , take a substrate made of glass fiber material, [0004] Step two, see Figure 25 , opening holes at desired locations on the fiberglass substrate, [0005] Step three, see Figure 26 , coated with a layer of copper foil on the back of the glass fiber substrate, [0006] Step 4, see Figure 27 , fill the conductive material in the position where the glass fiber substrate is punched, [0007] Step five, see Figure 28 , coated with a layer of copper foil on the front of the glass fiber substrate, [0008] Step six, see Figure 29 , coated with a photoresist film on the surfa...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L23/31H01L23/495H01L21/50
CPCH01L24/97H01L2224/73204H01L2924/01322H01L2924/181
Inventor 王新潮李维平梁志忠
Owner JCET GROUP CO LTD
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