Delay control circuit applied to memory unit and static random access memory

Abstract

The invention provides a delay control circuit applied to a memory unit. The delay control circuit applied to the memory unit comprises a control voltage-dividing circuit, a selecting circuit and a pull-down circuit, wherein voltage VCC is larger than a first preset value, a first NMOS (N-channel metal oxide semiconductor) tube and a second NMOS tube in the pull-down circuit work in a saturated region; and when the voltage VCC is smaller than the second preset value, the second NMOS tube works in a sub-threshold region. The delay control circuit provided by the invention can ensure that the second NMOS tube works in the sub-threshold region in case of a relatively low working voltage, has very small leakage current and can lower the discharge rate of a dummy bit line (DBL), so that the delay of a sense amplifier control signal SAEN can be achieved; when the SAEN signal reaches, a read-out BL and a read-out BLB of a memory array have a relatively large differential pressure dELTaV which is easily read out by the amplifier; and circuit functions are ensured to be correct and have no logic error.

Description

technical field [0001] The invention relates to the field of circuits, more specifically, to a delay control circuit applied to a storage unit and a static random access memory. Background technique [0002] With the continuous development of technology, SRAM is widely used due to the characteristic that its cells can save data without refreshing. Usually, for a normal SRAM, the working voltage is generally kept above 0.9Vcc, which can ensure good storage performance. However, due to the problem of low process technology or actual working voltage, logic errors and functional failures in specific read operations of the SRAM are caused. At the same time, the reduction of the operating voltage will inevitably lead to the reduction of the operating speed. [0003] see figure 1 , the existing technology usually adopts a method of changing the control signal of the sense amplifier to solve the above-mentioned problem, specifically, a dual column dummy cell is used to generate t...

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Problems solved by technology

[0005] In view of this, the present invention provides a delay control circuit applied to memory cells to overcome the problems of complex circuits, large areas and high costs caused by the use of dual-column dummy cells in the prior art

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