Manufacture method of trench MOS (Metal Oxide Semiconductor) transistor

Abstract

The invention relates to a manufacture method of a trench MOS transistor. The manufacture method comprises the following steps of: forming a trench in a silicon wafer; forming a gate structure in the trench; depositing an interlayer dielectric layer and forming patterns of two contact holes in the interlayer dielectric layer by etching, wherein one pattern corresponds to the contact hole contacted with an active region, and the other pattern is taken as a peripheral protection ring of a device; injecting ions B and P into the two contact holes, forming a well region and a source region in the active region, and meanwhile, forming a protection ring in a protection ring region; depositing tetraethoxysilane in the patterns of the two contact holes; depositing boro-phospho-silicate-glass in the patterns of the two contact holes; carrying out backflow on the boro-phospho-silicate-glass, and sealing the contact hole in the protection ring region; carrying out etching on the boro-phospho-silicate-glass to form a separator of the contact hole contacted with the active region, thereby shrinking an initial key size of the contact hole contacted with the active region as a final key size; etching a silicon substrate by taking tetraethoxysilane and the boro-phospho-silicate-glass as baffle layers to form the contact hole contacted with the active region; and forming a contact hole baffle layer, depositing metals, and etching the metals.

Description

technical field [0001] The invention relates to a semiconductor manufacturing process, more specifically, the invention relates to a method for manufacturing a trench type MOS transistor. Background technique [0002] Trench MOS (trench MOS) transistor, as a new type of vertical structure device, is developed on the basis of VDMOS (vertical double diffused metal-oxide semiconductor field effect transistor), both of which are high cell density devices. However, compared with the former, this structure has many performance advantages: such as lower on-resistance, low gate-to-drain charge density, thus low conduction and switching losses and fast switching speed. At the same time, since the channel of the trench MOS is vertical, the channel density can be further increased and the chip size can be reduced. [0003] figure 1 is a cross-sectional view of a conventional trench MOS transistor. Such as figure 1 As shown, a conventional trench MOS transistor includes a semiconduc...

AI Technical Summary

Problems solved by technology

However, since the three processes of well implantation, source implantation, and contact hole formation are completed in three steps, three photomasks are required to complete these three processes.

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