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Method to form solder deposits and non-melting bump structures on substrates
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A substrate and solder technology, applied in the field of flip-chip joints, can solve the problem of misalignment of the solder resin layer and the additional resin layer, etc.
Active Publication Date: 2013-04-17
ATOTECH DEUT GMBH
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This approach can lead to misalignment of the individually patterned solder resin layers and additional resin layers at small contact area sizes and narrow pitch distances
Method used
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example 1
[0156] Use an IC substrate that has an figure 2 a Contact pad structure.
[0157] The non-conductive substrate (102) is made of GX-13 material (manufacturer: Ajinomoto Fine-Techno Co., Inc), and the permanent resin layer (103) is made of GX-92 material (manufacturer: Ajinomoto Fine-Techno Co., Inc. ., layer height: 25 μm), and the contact pads are made of copper.
[0158] A temporary resin layer ( 104 ) (DuPont PM 200, height: 50 μm) was laminated onto the permanent resin layer ( 103 ).
[0159] Next, a contact area opening (105) is formed in one step with a UV laser through the temporary resin layer (104) and the permanent resin layer (103). The diameter of the contact area opening ( 105 ) is 100 μm.
[0160] Plating sequence according to figure 2 d to e. First, a first conductive seed layer ( 106 ) of copper is formed over the entire substrate surface. To this end, the surface is brought into contact first with an acidic solution comprising ionized palladium and then w...
example 2
[0168] A non-melting bump structure (112) composed of a tin-copperalloy is fabricated, the non-melting bump structure (112) having a solderable cladding (113) made of tin. Use an IC substrate that has an figure 2 a structure of at least one contact region.
[0169] The non-conductive substrate (102) is made of GX-13 material (manufacturer: Ajinomoto Fine-Techno Co., Inc), and the permanent resin layer (103) is made of GX-92 material (manufacturer: Ajinomoto Fine-Techno Co., Inc. ., layer height: 25 μm), and the contact pad ( 101 ) is composed of copper.
[0170] A temporary resin layer ( 104 ) (DuPont PM 200, height: 50 μm) was laminated onto the permanent resin layer ( 103 ).
[0171] Next, a contact area opening (105) is formed in one step with a UV laser through the temporary resin layer (104) and the permanent resin layer (103). The diameter of the contact area opening ( 105 ) is 100 μm.
[0172] Plating sequence according to figure 2 d to e. A first conductive seed...
example 3
[0181] A non-melting bump structure (112) of copper with a solderable cladding (113) of tin is fabricated.
[0182] An IC substrate is provided, comprising a non-conductive substrate (102), a contact area (101), a permanent resin layer (103) and a temporary resin layer (104) as used in Example 1.
[0183] The contact area opening (105) is formed in one step with a UV laser through the temporary resin layer (104) and the permanent resin layer (103). The diameter of the contact area opening ( 105 ) is 100 μm. Plating sequence according to figure 2 d to e. A first conductive seed layer (106) of copper is formed over the entire substrate surface. To this end, the surface is brought into contact first with an acidic solution comprising ionized palladium and then with a solution for electroless copper deposition.
[0184] Subsequently, a copper layer (107) is electroplated onto the first conductive seed layer (106) from a bath comprising: 45 g / l Cu 2+ as CuSO 4 , 50 ml / l H 2...
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Abstract
Described is a method of forming a metal or metalalloy layer onto a substrate comprising the following steps i) provide a substrate (102) including a permanent resin layer (103) on top of at least one contact area (101) and a temporary resin layer (104) on top of the permanent resin layer, ii) contact th entire substrate area including the at least one contact area with a solution suitable to provide a conductive layer (106) on the substrate surface and iii) electroplate a metal or metal alloy layer (107) onto the conductive layer.
Description
technical field [0001] The present invention relates to the formation of solder deposits by electroplating, in particular to flip chip packages, and more particularly to flip chip joints and board-to-board solder joints formed by electroplated metals or metal alloys (solder joint). Background technique [0002] Since the introduction of flip-chip technology by IBM in the early 1960s, flip-chip devices have been mounted on expensive ceramic substrates where the thermal expansion mismatch between the siliconchip and the ceramic substrate is less critical. Compared with wire bonding technology, flip chip technology can better pass higher packaging density (lower device outline) and higher electrical performance (shorter possible leads and lower inductance). On this basis, flip-chip technology has been industrially realized over the past 40 years using high-temperature solders (Controlled Collapse Chip Connection C4) on ceramic substrates. However, in recent years, driven by ...
Claims
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Application Information
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