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Method for improving power metal oxide semiconductor (MOS) device unclamped inductive switching (UIS) performance

A MOS device and performance technology, applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve problems such as device failure, achieve the effects of reducing turn-on, improving UIS performance, and improving UIS performance

Active Publication Date: 2013-05-08
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] In existing common power MOS devices, the Source (source) terminal is formed by a large dose of N-type impurity implantation. This method will form an N+P-type PN junction under the Sorce terminal. This form of PN junction In the UIS test process with MOS tubes, it is easier to turn on the parasitic NPN tube of the MOS tube, that is, the voltage drop on the P-base / N+ is greater than the turn-on voltage of the diode, so that the MOS device flows a large current, so that the device Failed in UIS tests

Method used

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  • Method for improving power metal oxide semiconductor (MOS) device unclamped inductive switching (UIS) performance
  • Method for improving power metal oxide semiconductor (MOS) device unclamped inductive switching (UIS) performance
  • Method for improving power metal oxide semiconductor (MOS) device unclamped inductive switching (UIS) performance

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Embodiment Construction

[0022] The method for improving the UIS performance of the PowerMOS device of the present invention includes:

[0023] (1) On the basis of the preparation process of the existing power MOS device, a large dose of source implantation (N-type impurity implantation) at the original PowerMOS source end was changed to 10 13 ~10 14 cm -2 A small dose of P-source implantation to form N-source, and a 4 × 10 15 ~8×10 15 cm -2 A large dose of As source is implanted to form N+source;

[0024] Among them, the schematic diagram of the structure after the first source injection, such as image 3 As shown, it can be seen that compared with ordinary products, the structure is basically the same, but the N-type impurity concentration of the first source injection is smaller, and this step is used to form a deeper N-source;

[0025] Schematic diagram of the structure after the second source injection, such as Figure 4 As shown, it can be seen that compared with the existing (traditional...

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Abstract

The invention discloses a method for improving power metal oxide semiconductor (MOS) device unclamped inductive switching (UIS) performance. The method for improving the power MOS device UIS performance includes the following steps: forming N+N- source electrode through twice of source electrode injecting on the basis of an existing power MOS device preparation technology, and replacing MOS parasitic N+PN pipe with N+N-PN pipe. According to the method for improving the power MOS device UIS performance, on the basis of the existing power MOS device technology, the number of an extra photomask is not increased, only is existing source injecting changed from one time to two times, and then MOS device with preferable UIS performance can be obtained.

Description

technical field [0001] The invention relates to a method for improving UIS (unclamped inductive switch) performance in the field of semiconductor integrated circuits, in particular to a method for improving UIS performance of a PowerMOS (power MOS) device. Background technique [0002] Power MOS (Metal Oxide Semiconductor) device is a device made of metal, oxide (SiO2 or SiN) and semiconductor materials. It can output a large working current (several amperes to tens of amperes) for devices of the power output stage. [0003] The structure of a typical Trench power MOS (metal oxide semiconductor) device is as follows figure 1 shown. The structure utilizes the area between P-base and N+ to form a conductive channel. When the gate is terminated with zero or negative voltage, the device is in an off state, and when the gate is terminated with a positive voltage, the device is turned on. [0004] In the UIS test process of the device, an unclamped inductor is generally connect...

Claims

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Application Information

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IPC IPC(8): H01L21/265H01L21/336
Inventor 罗清威吴晶左燕丽
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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