Plane type VDMOS production method

Abstract

The invention provides a plane type VDMOS production method. The plane type VDMOS production method comprises steps that a gate oxide grows on a silicon substrate; an N type polycrystalline silicon layer is deposited on the gate oxide; a silicon nitride is deposited on the N type polycrystalline silicon layer; the N type polycrystalline silicon layer and the silicon nitride, which are disposed on the left end and the right end of the upper part of the gate oxide, are removed; the body areas and the source areas of the plane type VDMOS are formed in the silicon substrate; a silicon dioxide layer is deposited on the upper surfaces of the left end and the right end of the gate oxide, the side surfaces of the N type polycrystalline silicon layer, the upper surface and the side surfaces of the silicon nitride; P type ions are injected from the silicon dioxide layer to the body area. The plane type VDMOS production method is advantageous in that the P type ions are effectively prevented from arriving at the N type polycrystalline silicon layer during the injection of the P type ions; and at the same time of improving the UIS performance of the plane type VDMOS, the threshold voltage of the plane type VDMOS is guaranteed, and therefore the performance of the plane type VDMOS is improved.

Description

technical field [0001] Embodiments of the present invention relate to the technical field of semiconductor device manufacturing, and in particular, to a method for manufacturing planar VDMOS. Background technique [0002] Planar vertical double-diffused metal-oxide-semiconductor transistor (abbreviation: planar VDMOS) is a power device that forms a channel through the difference in lateral diffusion distance formed after source ion and bulk ion implantation. It is widely used in the field of switching power supplies. [0003] In the manufacturing process of planar VDMOS, in order to reduce the resistance of the body region, the resistance of the body region and the hole region, and the short-circuit resistance of the source region and the body region, thereby improving the UIS performance of the device, it is necessary to use P after forming the silicon dioxide layer. The P-type ion implantation process implants P-type ions into corresponding positions in the device. [000...

AI Technical Summary

Problems solved by technology

[0004] figure 1 It is a schematic structural diagram of a planar VDMOS after P-type ion implantation in the prior art, such as figure 1 As shown, in the traditional process, after the silicon dioxide layer 9 is formed on the N-type polysilicon layer 4 and the gate oxide layer 3, when the P-type ion implantation is performed by the general injection process, the P-type ions will penetrate the silicon dioxide layer 9 and gate oxide layer 3, until it is implanted into the body region 7, since there is an N-type polysilicon layer 4 under the silicon dioxide layer 9, when P-type ions are implanted, the P-type ions will also reach the N-type polysilicon layer 4, but As the N-type polysilicon layer of the gate, the resistance is required to be as small as possible. Due to the compensation effect caused by the P-type ion implantation, the resistance of the N-type polysilicon layer 4 is increased, which in turn causes the threshold voltage drift of the planar VDMOS and the switching speed. decrease, which may eventually lead to failure of the planar VDMOS

Images