cmos formation method

Abstract

Disclosed is a formation method of a complementary metal oxide semi-conductor transistor (CMOS). The formation method of the CMOS comprises that a gate medium layer is formed on the surface of a semi-conductor substrate in a first sector and a second sector. A first polycrystalline silicon layer is formed on the surface of the gate medium layer in the first sector. A second polycrystalline silicon layer is formed on the surface of the gate medium layer in the second sector. A medium layer is formed on the surface of the semi-conductor substrate and is level with the surface of the first polycrystalline silicon layer and the surface of the second polycrystalline silicon layer. A first metal layer is formed on the surface of the medium layer. The first polycrystalline silicon layer and the second polycrystalline silicon layer are covered by the first metal layer. A separating layer is formed on the surface of the first metal layer covering the first sector. A second metal layer is formed on the surface of the separating layer in the first sector and the surface of the first metal layer in the second sector. A first metal silicide layer is formed in the first polycrystalline silicon layer by using the annealing technology. A second metal silicide layer is formed in the second polycrystalline silicon layer. Various steps of sedimentation and etching are not needed and technology steps are saved.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a CMOS forming method. Background technique [0002] Complementary metal-oxide-semiconductor (CMOS) transistors are the basic units in modern logic circuits, which include PMOS and NMOS, and each PMOS (NMOS) transistor is located on a doped well and is surrounded by gates on both sides. The p-type (n-type) electrode / drain region in the substrate and the channel (Channel) between the source region and the drain region are formed. [0003] With the continuous advancement of CMOS technology, metal gate electrode technology is applied to CMOS manufacturing to overcome the negative effects of doped polysilicon, which include: gate electrode loss, high impedance, and gate electrode and high-k value gate dielectric. incompatibility. [0004] Since each metal should have a unique work function in a MOS device, the work function is a key material parameter affecting the thresh...

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Problems solved by technology

[0005] However, the dual metal gate needs to use different metals for NMOS and PMOS, and the process is complicated. Therefore, in the Chinese patent document with the publication number CN10149654A, a method for forming a fully silicided gate electrode is disclosed, which uses different silicides Phase state to control the effective work function of PMOS and NMOS transistors, resulting in a suitable threshold voltage for both NMOS and PMOS

[0006] However, the above-mentioned method for forming the fully silicided gate electrode is complex in process, and the product yield rate and product performance are low.

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