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Test structure used for evaluating organic photo conductor (OPC) effects

A technology for testing structures and devices, applied to electrical components, electrical solid devices, circuits, etc., can solve problems that cannot be directly reflected on the influence of filleting effects on device characteristics

Active Publication Date: 2013-05-08
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0008] So how to accurately evaluate the correction effect of the OPC scheme used? The current evaluation method only stays in the collection of graphic size data of the physical structure. Influence of Keratinization Effect on Device Characteristics

Method used

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  • Test structure used for evaluating organic photo conductor (OPC) effects
  • Test structure used for evaluating organic photo conductor (OPC) effects
  • Test structure used for evaluating organic photo conductor (OPC) effects

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no. 1 example

[0046] The first embodiment of the present invention is a test structure for evaluating the effect of CMOS polysilicon layer OPC (Optical Proximity Correction), the test structure includes 2*N CMOS devices (NMOS or PMOS), and N is greater than or equal to 3 According to the set size, it is produced by a corresponding set of CMOS semiconductor process including OPC process. The size is set based on the corresponding design rules of this set of CMOS semiconductor process. The specific value of the size is different due to different sets of CMOS semiconductor process. same;

[0047] N CMOS devices in the 2*N CMOS devices are used as an inspection group;

[0048] N CMOS devices in the 2*N CMOS devices are used as a reference group;

[0049] For the CMOS devices in the inspection group, the distance between the L-shaped polysilicon 102 and the single crystal silicon active region 101 (such as figure 2 A) marked above is equal to e;

[0050] For the CMOS devices in the reference...

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Abstract

The invention discloses a test structure used for evaluating organic photo conductor (OPC) effects of a complementary metal-oxide-semiconductor (CMOS) polycrystalline silicon layer. The test structure comprises 2N pieces of CMOS devices; a corresponding CMOS semi-conductor process including the OPC process is adopted for production according to prearranged sizes; the 2N pieces of the CMOS devices serve as an array which is divided into two groups according to different layout modes; one group serves as an inspection group, and the other group serves as a reference group, in terms of the CMOS devices in the inspection group; the distance between L-shaped polycrystalline silicon and active areas of monocrystalline silicon is equal to e, and in terms of the CMOS devices in the reference group, the distance between L-shaped polycrystalline silicon and active areas of monocrystalline silicon is larger than or equal to 2e; and e is the minimum distance between the L-shaped polycrystalline silicon and the active area of the monocrystalline silicon of the same CMOS device in the design rule of the CMOS semi-conductor process. The invention further discloses a test structure used for evaluating the OPC effects of active area layers of the CMOS monocrystalline silicon. The test structure can visually detect whether the OPC eliminates influences of corner round corner effects on device characteristics according to device electric characteristic data.

Description

technical field [0001] The invention relates to semiconductor technology, in particular to a test structure for evaluating the OPC effect, including a test structure for evaluating the OPC effect of a CMOS polysilicon layer, and a test structure for evaluating the OPC effect of a CMOS single crystal silicon active region layer. Background technique [0002] Photolithography is the main process of integrated circuit manufacturing. The task of photolithography process is to realize the transfer of the pattern on the mask plate to each layer of material on the silicon surface. The projected light propagates to the silicon wafer after passing through the mask pattern. The mask pattern is equivalent to an obstacle on the propagation route for the light wave, so that the lithography pattern related to the mask pattern is obtained on the silicon wafer. According to the principle of light wave diffraction and interference, light waves will diffract when passing through the mask, and...

Claims

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Application Information

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IPC IPC(8): H01L23/544
Inventor 刘梅朱冬慧陈福成
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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