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Data communication circuit arranged among a plurality of processors and adopting data driving mechanism

A multi-processor, data communication technology, applied in the combination of a variety of digital computers, etc., to achieve the effect of reducing difficulty, strong scalability, and high parallel communication capabilities

Inactive Publication Date: 2013-07-24
SHANGHAI UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

At present, there are many different designs for the interconnection and communication of multi-core processors, but there are still many problems in how to effectively deal with the cooperation between a large number of multi-core systems and the communication of a large number of processor cores.

Method used

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  • Data communication circuit arranged among a plurality of processors and adopting data driving mechanism
  • Data communication circuit arranged among a plurality of processors and adopting data driving mechanism
  • Data communication circuit arranged among a plurality of processors and adopting data driving mechanism

Examples

Experimental program
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Effect test

Embodiment 1

[0029] Such as figure 1 As shown, the inter-processor data communication circuit using the data-driven mechanism proposed by the present invention includes a crossbar switch matrix (1), 4 data stream memories (2 0 ,2 1 ,2 2 ,2 3 ), four matching circuits (3 0 、3 1 、3 2 、3 3 ). Its characteristics are: when sending data, the source CPU passes through the matching circuit (3 0 、3 1 、3 2 、3 3 ) to send data to the crossbar matrix (1) to realize data transmission; when receiving data, firstly, the source data is sent to the corresponding output port of the crossbar matrix (1) after the path is selected by the crossbar matrix (1), and the output data enters data stream memory (2 0 ,2 1 ,2 2 ,2 3 ), through dedicated memory for streaming data (2 0 ,2 1 ,2 2 ,2 3 ) After the integrity check, the function number and data are taken out and sent to the corresponding destination CPU.

Embodiment 2

[0031] This embodiment is basically the same as Embodiment 1, and the special features are as follows:

[0032] , data flow memory

[0033] see figure 2 , the data flow memory is a special memory, mainly composed of FIFO storage, data processing module, label update module, RAM data memory and FIFO function memory. Among them, FIFO storage is mainly used to store the input data, so that the data can be received and transmitted correctly; the data processing module is composed of data segment extraction, address generator, decoder, bit expansion and control logic, and takes out the input data. The function number, data number and data, and the corresponding address is generated by the address generator, so that the data is transmitted to the relevant function module for corresponding operation, and the corresponding operand label is generated; the label update module is generated by the label device, tag function data table registers and other control logic. Its main functi...

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Abstract

The invention relates to a data communication circuit arranged among a plurality of processors and adopting a data driving mechanism. The data communication circuit arranged among the plurality of processors and adopting the data driving mechanism comprises a crossbar switch matrix, four data stream memorizers and four match circuits. As shown in the figure, when data transfer is sent, a source CPU sends data to the crossbar switch matrix to achieve data transmission according to a preset protocol through a match circuit which is connected with the source CPU. When data are received, source data are transmitted to a corresponding output port of the crossbar switch matrix after the source data pass through the crossbar switch matrix to carry out path selection, the output data enter a data flow memory (DFM), and function numbers and the data are extracted and are transmitted to corresponding goal CPUs after completeness detection of the DFM is carried out on the data. The data communication circuit arranged among the plurality of processors and adopting the data driving mechanism can well solve the problem of a communication bottleneck which appears in a multi-core structure.

Description

technical field [0001] The invention relates to a multi-processor data communication circuit using a data-driven mechanism, in particular to an arrayable high-parallel data-driven communication circuit involving data stream driving technology and crossbar matrix technology. Background technique [0002] Multi-core processor refers to the technology of integrating more than two processor cores on one chip to enhance computing performance. CMP (on-chip multiprocessor) improves system performance by distributing workloads across multiple CPU cores and relying on high-speed on-chip interconnects and high-bandwidth pipelines to memory and input / output (I / O). Multi-core processors, which offer performance and productivity advantages over current single-core processors, will eventually become a widespread computing paradigm. [0003] Since the development of processors, the intervention of factors such as heat generation and interference has made the frequency of a single processo...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F15/17
Inventor 毕卓王镇徐云川孔维利张莹
Owner SHANGHAI UNIV
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