Method for plasma-activated conformal film deposition on substrate surfaces
A technology of substrate surface and plasma, applied in metal material coating process, coating, gaseous chemical plating, etc., can solve the problems of prolonging the distribution time, insufficient device performance, chemical or electrical, waste, etc.
Active Publication Date: 2017-04-12
NOVELLUS SYSTEMS
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Problems solved by technology
Some ALD processes may not saturate the wafer, resulting in incomplete film deposition, film islanding, and film thickness variance on the wafer
Some solutions to incomplete film deposition include longer dosing times to saturate the wafer surface with film precursor
But prolonged dosing times waste valuable precursors during the membrane nucleation phase
The added effect of prolonging processing time is reducing processing tool throughput, requiring installation and maintenance of additional processing tools to support the production line
Furthermore, films prepared by such methods may have physical, chemical, or electrical properties that provide insufficient device performance
Method used
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[0050] Fabrication of semiconductor devices typically involves depositing one or more thin films on non-planar substrates in an integrated fabrication process. In some aspects of the integration process, it may be useful to deposit thin films that conform to the topography of the substrate. For example, a silicon nitride film can be deposited on top of an elevated gate stack as a spacer to protect the lightly doped source and drain regions from subsequent ion implantation processes.
[0051] Among the spacer layer deposition processes, a chemical vapor deposition (CVD) process may be used to form a silicon nitride film on a non-planar substrate, which is then anisotropically etched to form an upper spacer structure. However, as the distance between gate stacks decreases, the species transport limitations of the CVD gas phase reaction may lead to a "bread-loafing" deposition effect. These effects generally result in thicker deposits on the top surface of the gate stack and thi...
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Abstract
A method of depositing a film on a substrate surface includes providing a substrate in a reaction chamber; selecting a silicon-containing reactant from a precursor group consisting of di-tert-butyl diazidosilane, bis(ethylmethylamido)silane, bis(diisopropylamino)silane, bis(tert-butylhydrazido)diethylsilane, tris(dimethylamido) silylazide, tris(dimethylamido)silylamide, ethylsilicon triazide, diisopropylaminosilane, and hexakis(dimethylamido)disilazane; introducing the silicon-containing reactant in vapor phase into the reaction chamber under conditions allowing the silicon-containing reactant to adsorb onto the substrate surface; introducing a second reactant in vapor phase into the reaction chamber while the silicon-containing reactant is adsorbed on the substrate surface, and wherein the second reactant is introduced without first sweeping the silicon-containing reactant out of the reaction chamber; and exposing the substrate surface to plasma to drive a reaction between the silicon-containing reactant and the second reactant on the substrate surface to form the film.
Description
[0001] Cross References to Related Applications [0002] This application claims the benefit of and priority to patent application 61 / 598,547, filed February 14, 2012. The entire disclosure of this patent application is incorporated into this application by reference. [0003] This application is related to U.S. Patent Application No. 13 / 084,399, filed April 11, 2011, U.S. Patent Application No. 13 / 084,305, filed April 11, 2011, U.S. Patent Application No. 13 / 084,305, filed April 11, 2011 Application No. 13 / 083,827, which patent applications are hereby incorporated by reference in their entirety. Background technique [0004] Various thin film layers of semiconductor devices can be deposited using atomic layer deposition (ALD) processes. Some ALD processes may fail to saturate the wafer, resulting in incomplete film deposition, film islanding, and film thickness variance on the wafer. Some approaches to address incomplete film deposition include longer dosing times to satur...
Claims
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IPC IPC(8): C23C16/44
Inventor 阿德里安·拉瓦伊马克·J·萨利丹尼尔·莫泽拉杰什·奥德德拉拉维·卡尼奥莉亚
Owner NOVELLUS SYSTEMS