Method and relevant device for achieving metal mutual connection through preparation of micro-protruding-points with superfine spaces

A metal interconnection and micro-bump technology, applied in the field of microelectronics, can solve problems such as undercutting and pitch reduction, and achieve the effects of reduced flatness, reduced requirements, and low cost

Active Publication Date: 2013-08-21
NAT CENT FOR ADVANCED PACKAGING
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0005] In view of this, the purpose of the present invention is to propose a new method for realizing the metal interconnection of semiconductor or solid devices by preparing ultra-f

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  • Method and relevant device for achieving metal mutual connection through preparation of micro-protruding-points with superfine spaces
  • Method and relevant device for achieving metal mutual connection through preparation of micro-protruding-points with superfine spaces
  • Method and relevant device for achieving metal mutual connection through preparation of micro-protruding-points with superfine spaces

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Embodiment Construction

[0036] The existing microbump preparation technology includes deposition of metal seed layer, coating and exposure, electroplating and etching of metal seed layer, wherein coating and exposure, electroplating and etching of metal seed layer all affect the reduction of bump pitch. Especially in the etching of the seed layer, when the pitch of the bumps becomes smaller, the undercutting is very serious, causing the bumps to fall off, and further reducing the distance between the bumps is restricted.

[0037] In order to further reduce the distance between the micro-bumps, it is extremely important to overcome the undercut around the micro-bumps after the seed layer is etched. The invention adopts the improved damascene process flow to prepare the micro-bumps, avoids the wet etching process and has no bump undercutting phenomenon. The new process first deposits the silicon carbide etch stop layer and the electrolyte layer, coats the glue, etches holes in the electrolyte layer by ...

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Abstract

The invention discloses a method for achieving metal mutual connection through preparation of micro-protruding-points with superfine spaces and a relevant device for achieving the metal mutual connection through the preparation of the micro-protruding-points with the superfine spaces. The method includes the steps: first depositing silicon carbide to etch a stop layer and an electrolyte layer, gluing, conducting etching on the electrolyte layer to form a hole in a dying mode, depositing a metal seed layer, filling metal, utilizing CMP to clear metal on a face, conducting etching on the electrolyte layer, forming a metal exposed head structure and plating anti-oxidative or low-melting-point metal, and then conducting bonding. The method avoids protruding point drilling etch, the spaces of the protruding points can be reduced into a plurality of micron sizes and even into a plurality of nanometer sizes which are far smaller than the sizes of the spaces of existing protruding points. Due to fact that a metal end face is higher than the electrolyte layer, the phenomenon of depressions in the surface of metal caused by the CMP can be overcome, during bonding, complete contacting between upper metal and lower metal can be guaranteed through plastic deformation, and requirements to evenness are lowered after wafers undergo the CMP. Bonding can be completed under low temperature through a general hot-pressing method. The relevant device has the advantages of being low in cost.

Description

technical field [0001] The invention belongs to the technical field of microelectronics, relates to a metal interconnection process for semiconductor or solid devices, in particular to a method for realizing the metal interconnection of semiconductor or solid devices by preparing ultra-fine-pitch micro-bumps and the metal interconnection process made by the method. corresponding devices. Background technique [0002] With the continuous advancement of microelectronics technology, the feature size of integrated circuits has been continuously reduced and the interconnection density has been continuously increased. At the same time, users' requirements for high performance and low power consumption continue to increase. In this case, the way to improve the performance by further reducing the line width of the interconnection is limited by the physical characteristics of the material and the equipment process, and the resistance-capacitance (RC) delay of the two-dimensional int...

Claims

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Application Information

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IPC IPC(8): H01L21/768H01L21/603H01L23/485
CPCH01L2224/11
Inventor 张文奇
Owner NAT CENT FOR ADVANCED PACKAGING
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