A chip architecture suitable for two-dimensional barcode decoding chips
A decoding chip and two-dimensional barcode technology, applied in the field of barcode recognition, can solve the problems of high production cost, limited processor computing performance and software algorithm optimization degree, high system power consumption, etc.
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[0032] The present invention will be further described below in conjunction with specific examples.
[0033] What the present invention proposes is a chip architecture suitable for two-dimensional barcode decoding chips based on Leon3, and the overall architecture is as follows figure 1 shown. The chip architecture adopts a system-on-a-chip (SoC, SystemonaChip) solution based on the Leon3 processor. Leon3 is developed by the European Space Agency and is a 32-bit SPARCV8 instruction set architecture processor suitable for embedded system or SoC system design. , is a highly configurable high-performance, low-complexity, low-power processor.
[0034] The overall architecture of the two-dimensional barcode decoding chip mainly includes three parts: GRLIB library, AMBA bus architecture, and custom IP core. The GRLIB library is mainly used to build the Leon3 system environment, including core processor Leon3, debugging unit, memory management control and other modules; the AMBA bu...
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