Fabrication method of wafer level semiconductor package and fabrication method of wafer level packaging substrate

Abstract

The invention relates to a fabrication method of a wafer level semiconductor package and a fabrication method of a wafer level packaging substrate. The fabrication method of the wafer level semiconductor package includes: forming on a carrier a first dielectric layer having first openings exposing portions of the carrier; forming a circuit layer on the first dielectric layer, a portion of the circuit layer being formed in the first openings; forming on the first dielectric layer and the circuit layer a second dielectric layer having second openings exposing portions of the circuit layer; forming conductive bumps in the second openings; mounting a semiconductor component on the conductive bumps; forming an encapsulant for encapsulating the semiconductor component; and removing the carrier to expose the circuit layer. By detecting the yield rate of the circuit layer before mounting the semiconductor component, the invention avoids discarding good semiconductor components together with packages as occurs in the prior art, thereby saving the fabrication cost and improving the product yield.

Description

technical field [0001] The invention relates to a method for manufacturing a semiconductor package, in particular to a method for manufacturing a wafer-level semiconductor package with improved precision and a method for manufacturing a wafer-level package substrate. Background technique [0002] With the vigorous development of the electronic industry, electronic products are gradually moving towards the trend of multi-function and high performance. In order to meet the packaging requirements of miniaturization of semiconductor packages, a technology of wafer level packaging (WLP) has been developed. [0003] US Pat. No. 6,452,265 and US Pat. No. 7,202,107 provide a method for wafer level packaging. see Figure 1A to Figure 1E , which is a schematic cross-sectional view of a conventional wafer-level semiconductor package 1 manufacturing method. [0004] Such as Figure 1A As shown, a thermal release tape 11 is formed on a carrier board 10 . [0005] Such as Figure 1B ...

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Problems solved by technology

[0009] However, in the existing manufacturing method of the semiconductor package 1, the thermal release adhesive layer 11 is flexible, and its coefficient of thermal expansion (Coefficient of thermal expansion, CTE) in the molding process and the lateral thrust of the encapsulant 13 will It affects the fixing accuracy of semiconductor components 12 (such as chips). Therefore, when the size of the carrier board 10 to be rearranged is larger, the positional tolerance between each semiconductor component 12 is also increased, resulting in the yield rate of the RDL and bump processes. loss

[0010] In addition, in the existing manufacturing method, the encapsulant 13 is first formed to encapsulate the semiconductor component 12, and then the RDL process is performed. If the yield rate of the circuit structure 14 is detected to be poor in the subsequent test, the semiconductor package needs to be 1 Discarding as a whole, that is, scrapping good semiconductor components 12 together, so the existing process is easy to waste materials, that is, discarding good semiconductor components 12, resulting in an increase in cost, so it is not in line with economic benefits at all

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