Test path selection method and corresponding wafer test method

Abstract

The invention provides a test path selection method which includes the first step of forming valid dies and invalid dies on an arranged wafer, the second step of forming a wafer mapping picture, the third step of marking the positions of the valid dies and the invalid dies on the wafer mapping picture according to the positions of the valid dies and the invalid dies, the fourth step of enabling multi-circuit-block needle card pictures to be arranged repeatedly on the dies of the wafer mapping picture and filling the wafer mapping picture, wherein the multi-circuit-block needle card pictures at least comprise a first needle card identification mark and a second needle card identification mark, the fifth step of eliminating the multi-circuit-block needle card pictures fully occupying the invalid dies on the wafer mapping picture and reserving the multi-circuit-block needle card pictures at least occupying one valid die, and the sixth step of enabling the dies corresponding to the first identification marks in each multi-circuit-block needle card picture reserved on the wafer mapping picture to be connected into a straight line, and obtaining a test path. The invention further provides a wafer test method. The test path selection method and the corresponding wafer test method shorten the distance of needle card displacement in the testing process, save needle card displacement time, and improve testing efficiency of wafers.

Description

technical field

[0001] The invention belongs to the technical field of semiconductor testing, and in particular relates to a testing path selection method and a corresponding wafer testing method. Background technique

[0002] After the circuits are manufactured on the wafer by semiconductor integration technology, it is necessary to test the wafer in which the circuits are manufactured before the wafer is diced. This kind of test generally tests the circuit blocks in the wafer one by one by moving the probe (Probe) on the surface of the wafer.

[0003] In the existing technology, the general testing process is as follows: the wafer with the circuit manufactured is placed on the probe station, and the probe station has probes and sensors, and the probe probes the wafer through the sensor to obtain the size of the wafer. And the position of the wafer around the probe station, combined with the progressive scanning method to test the circuit blocks (ie dies) in the wafer: ...

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