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Semiconductor wafers comprising gallium nitride with one or more interlayers of silicon nitride therein

A semiconductor, wafer technology, applied in the field of semiconductor wafers including gallium nitride having one or more silicon nitride interlayers therein

Active Publication Date: 2016-08-17
INTELLEC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, considering, for example, the fabrication of GaN-based LEDs on Si substrates via low-cost routes, additional procedures such as ex-situ patterning before growth are not preferred, and a method is required to simultaneously obtain Crack-free layers, low threading dislocations, and flat wafers

Method used

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  • Semiconductor wafers comprising gallium nitride with one or more interlayers of silicon nitride therein
  • Semiconductor wafers comprising gallium nitride with one or more interlayers of silicon nitride therein
  • Semiconductor wafers comprising gallium nitride with one or more interlayers of silicon nitride therein

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Embodiment 1

[0068] In this embodiment, in a 6×2” Aixtron CCS reactor using a 6×2” or 1×6” susceptor (susceptor), the metal-organic vapor phase epitaxy (MOVPE) is used in 2 inches or 6 inches. GaN structure is grown on a Si(111) substrate 5. Trimethylgallium (TMG), Trimethylaluminum (TMA) and Trimethylindium (TMI) are used as Group III precursors, while ammonia is used as a nitrogen source 。 Silane (SiH 4 ) And cyclopentadienyl magnesium (Cp 2 Mg) is used as a source of n-type and p-type dopants, respectively.

[0069] A flat, crack-free and uniform GaN-based LED structure is grown on a 6-inch Si(111) substrate 5 by metal organic vapor phase epitaxy (MOVPE). First, the provided Si(111) substrate 5 is annealed in a reactor to remove the natural oxide layer.

[0070] Subsequently, an AlN nucleation layer 10 is grown, which prevents Ga from reacting with the Si substrate. Then, an AlGaN buffer layer 15 is grown to control stress. The AlN nucleation layer 10 and the graded AlGaN buffer layer 15 ...

Embodiment 2

[0080] Commercially available A TT sensor (Laytec GmbH) was used to give emissivity-corrected real-time temperature and wafer curvature measurements, and an Argus (Aixtron) in-situ temperature measuring instrument was installed on the top of the reactor to provide a complete temperature map of the wafer. figure 2 Shows traces of wafer curvature during wafer manufacturing.

[0081] Such as figure 2 As shown, the curvature of the wafer has been changing throughout the process.

[0082] Between 1000s and 3000s, the substrate is annealed and reaches a plateau at 25 / km. Then a 200nm AlN nucleation layer is formed, which increases the concave shape of the wafer. The AlGaN buffer layer is formed at 7500s, and then the GaN layer contains a single interlayer to a total thickness of 1.3 μm. A Si-doped GaN layer is formed at 12500. Between 14000s and 18000s, the InGaN-GaN multiple quantum well (MQW) is formed before the wafer composite is allowed to cool. During cooling, the curvature d...

Embodiment 3

[0092] The graded AlGaN buffer layer was grown on the AlN / Si template, and then a 300nm thick GaN layer was grown at 1020°C. Then lower the temperature to 950℃ for SiN deposition x It is sandwiched and regrown at 970°C to form multi-faceted islands, and then changed to 1050°C for slow growth of the GaN layer to fuse the film. After the film is completely fused, the growth conditions are set to faster GaN growth. Depositing SiN x The thickness of GaN required for the complete fusion film depends on SiN x The deposition time of IL and the growth conditions for GaN to grow on top. About 6x10 8 cm -2 The TD density is obtained with a flat crack-free wafer. The preferred TD density is less than 5x10 9 cm -2 , More preferably less than 1x10 9 cm -2 , More preferably less than 8x10 8 cm -2 .

[0093] After growing the AlGaN buffer layer, grow a nominally undoped 100-400nm thick GaN, and then deposit SiN x Interlayer, and further grow GaN. Keep the two GaN regions (~600nm in total) no...

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Abstract

A semiconductor wafer comprising a substrate layer and a first GaN layer having one or more SiNx interlayers therein, wherein in the first GaN layer at least one SiNx interlayer has GaN penetrated through one or more portions of said SiNx interlayer and preferably has a thickness of from 0.5 to 10 nm.

Description

Technical field [0001] The present invention relates to semiconductor materials and their application in wafer-form for forming light emitting diodes (LEDs) or other optoelectronic devices. In addition, the present invention relates to a method of using wafers to construct high-quality optoelectronic devices. In particular, the present invention relates to an improved LED that has a silicon substrate (substrate, substrate) that minimizes dislocation defects and wafer bending / cracking when a large support wafer is used. Background technique [0002] Optoelectronic devices are well known, and it is also well known that it is desirable for such devices to minimize the occurrence of defects in the semiconductor layer forming part of the device structure. Common defects in LEDs include, for example, threading (blade or spiral) dislocations that cause a reduction in the luminous efficiency of the final product. Due to the non-radiative recombination that occurs at dislocations and de...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/205H01L21/02
CPCB82Y20/00H01L21/02381H01L21/0242H01L21/02458H01L21/02488H01L21/02505H01L21/0251H01L21/0254H01L21/02573H01L21/0262H01L31/035236H01L31/075H01L31/1852H01L31/1856H01L33/007H01L33/12H01L33/32Y02E10/544Y02E10/548H01L21/02389H01L21/2015H01L31/03048
Inventor 科林·汉弗莱斯克利福德·麦卡利斯门诺·卡珀斯刘震宇朱丹丹
Owner INTELLEC