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Method for Improving the Stability of Polysilicon Gate Etching Process

A polysilicon gate and stability technology, applied in semiconductor devices and other directions, can solve the problems of insufficient etching selection ratio of polycrystalline silicon gate and gate oxide layer, damaged active area, etc., to overcome the insufficient etching selection ratio. , Avoid damage to the active area, improve the stability of the etching process and the electrical properties of the product

Active Publication Date: 2016-09-07
SHANGHAI HUALI MICROELECTRONICS CORP
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Problems solved by technology

[0011] In order to overcome the above problems, the purpose of the present invention is to avoid the phenomenon that the active region is damaged due to the insufficient etching selectivity ratio of the polysilicon gate and the gate oxide layer, thereby further improving the stability of the polysilicon etching process

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  • Method for Improving the Stability of Polysilicon Gate Etching Process
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  • Method for Improving the Stability of Polysilicon Gate Etching Process

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Embodiment Construction

[0040] Embodiments embodying the features and advantages of the present invention will be described in detail in the following description. It should be understood that the invention can have various changes in different examples without departing from the scope of the invention, and that the descriptions and illustrations therein are illustrative in nature rather than limiting the invention.

[0041] The following is attached Figure 7-15 , the method for improving the stability of the polysilicon gate etching process of the present invention will be further described in detail through specific embodiments. It should be noted that the drawings are all in a very simplified form, using imprecise scales, and are only used to facilitate and clearly achieve the purpose of assisting in describing the embodiments of the present invention.

[0042] see Figure 7-15 , Figure 7 It is a schematic flowchart of a method for improving the stability of polysilicon gate etching process i...

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Abstract

The present invention provides a method for improving the stability of the etching process of a polycrystalline silicon gate. The method comprises: providing a semiconductor substrate, and forming a gate oxide on the semiconductor substrate; forming an oxide layer on the gate oxide; coating the oxide layer with a player of photoresist, and after etching, removing the oxide layer in the area of the polycrystalline silicon gate and removing the photoresist; growing a polycrystalline silicon layer on the semiconductor substrate; and after photolithography and etching, forming the polycrystalline silicon gate in the polycrystalline silicon layer. According to the method provided by the invention, in the process of etching the polycrystalline silicon gate, damage on the active region caused by insufficiency of the etching selectivity ratio of the polycrystalline silicon gate and the gate oxide is prevented by the oxide layer, so that the stability of the etching process of the polycrystalline silicon gate and the electrical performance of the product are improved.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a method for improving the stability of a polysilicon gate etching process. Background technique [0002] With the development of semiconductor technology, the size of semiconductor devices is getting smaller and smaller, especially in the process of 65nm and below, in order to meet the electrical requirements, the gate oxide layer becomes thinner and thinner, and the etching of polysilicon gate Process requirements are getting higher and higher. [0003] Such as Figure 1-6 as shown, figure 1 is a schematic flow chart of a conventional polysilicon gate etching method, Figure 2-6 A schematic diagram of a cross-sectional structure formed by each preparation step of a conventional polysilicon gate etching method, including: [0004] Step S11: See figure 2 , providing a semiconductor substrate 101, forming a gate oxide layer 102 on the semiconductor substr...

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/28
Inventor 唐在峰方超任昱张旭昇
Owner SHANGHAI HUALI MICROELECTRONICS CORP