Semiconductor wafer and method for manufacturing same

A manufacturing method and semiconductor technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, manufacturing tools, etc., to achieve the effect of improving productivity and yield

Active Publication Date: 2014-01-01
SHIN-ETSU HANDOTAI CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Also, the thickness of the semiconductor wafer varies greatly between 0.5 and 1 mm from the outer peripheral end of the wafer. In the futu

Method used

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  • Semiconductor wafer and method for manufacturing same
  • Semiconductor wafer and method for manufacturing same
  • Semiconductor wafer and method for manufacturing same

Examples

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Example Embodiment

[0105] (Example 1)

[0106] The single crystal rod was sliced ​​into a silicon wafer with a diameter of 300 mm, and the silicon wafer was chamfered (chamfered) and flattened. Then, the double-sided grinding machine described in JP 2003-285262 A was used and adjusted to the following conditions to perform double-sided grinding: between the center of the semiconductor wafer and the start position of the outer peripheral sag, the thickness direction of the semiconductor wafer The amount of displacement becomes 100 nm or less, and the center of the semiconductor wafer becomes a convex shape. At this time, since it is not preferable that the outer periphery collapses due to double-sided polishing, a rigid foamed urethane pad is used for the polishing cloth, specifically, Nitta Haas MH-S15A is used. The polishing slurry is adjusted to a pH of 10.5 with abrasive grains composed of colloidal silica with a particle size of 0.05 μm, and the load is 200 g / cm. 2 Come for grinding. In order...

Example Embodiment

[0107] (Example 2)

[0108] The surface temperature of the polishing cloth during polishing will accumulate heat during polishing, so the temperature of the center part of the polishing cloth will be relatively higher than the outer peripheral part. This temperature difference will affect the polishing rate, so by controlling the range of this area, the starting position of the sag can be controlled. In Example 2, in addition to adjusting the polishing load, the number of revolutions of the polishing head, and the slurry supply temperature in a manner that does not change the average in-plane grinding amount of the wafer, the high temperature area is increased to be greater than that of Example 1, and to make The starting position of the outer peripheral sag is closer to the center side (35mm from the outer peripheral end to the center side) than the outer peripheral part of the semiconductor wafer that is the measurement object of ESFQR. The one side of the silicon wafer is chem...

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Abstract

A semiconductor wafer having sag formed at an outer periphery at the time of polishing, wherein a displacement of the semiconductor wafer in a thickness direction is 100 nm or less between a center and a outer peripheral sag start position of the semiconductor wafer, and the center of the semiconductor wafer has a convex shape, an amount of outer peripheral sag of the semiconductor wafer is 100 nm or less, and the outer peripheral sag start position is away from an outer peripheral portion of the semiconductor wafer toward the center or 20 mm or more away from an outer peripheral end of the semiconductor wafer toward the center, the outer peripheral portion being a measurement target of ESFQR.

Description

technical field [0001] The invention relates to a semiconductor wafer and a manufacturing method thereof. The semiconductor wafer satisfies two or more flatness parameters. Background technique [0002] In recent years, with the development of miniaturization, it is also required to have a flat wafer (wafer) shape up to the outer periphery of the semiconductor wafer. In addition to GBIR (Global Backsurface-referenced Ideal plane / Range, the overall back surface-reference Ideal plane / range), SFQR (Site Frontsurface referenced least sQuares / Range, site front referenced least squares / range), SBIR (Site Backsurface-referenced Ideal plane / Range, site back surface-reference ideal plane / range), etc., have also started The following new indicators are used: ROA (Roll Off Amount, also known as Edge Roll Off Amount) for evaluating the flatness of the peripheral portion of a semiconductor wafer, ESFQR (Edge Site Frontsurface referenced least sQuares / Range , frontal benchmark least squa...

Claims

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Application Information

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IPC IPC(8): H01L21/304
CPCH01L21/0201H01L21/02024H01L29/34B24B37/34H01L21/02H01L21/304
Inventor 佐藤三千登
Owner SHIN-ETSU HANDOTAI CO LTD
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