Dummy comprehensive optimization method based on CMP simulation model

Abstract

The invention belongs to the field of manufacturability design of semiconductors and particularly relates to a dummy comprehensive optimization method based on a CMP simulation model for the copper-connection dummy metal filling technology. According to the method, the height morphology of the surface of a chip after undergoing CMP is obtained through full-chip CMP simulation, and an effective hot spot region with intense height changes is obtained; step-by-step dummy filling and fast CMP simulation of local regions are carried out iteratively in the effective hot spot region to gradually eliminate hot spots; finally, it is assured that no effective hot spot exists through the full-chip CMP simulation. Compared with a dummy comprehensive method based on rules, the dummy comprehensive optimization method based on the CMP simulation model can ensure that the height deviation of a layout after dummy filling and the CMP is within a given deviation threshold, and the dummy filling amount is small. Experiments show that in the same filling amount, the mean-square error ratio of the height morphology obtained respectively through the SMDF dummy filling method and the FMF dummy filling method is 58% smaller than that of the height morphology obtained through the dummy filling method driven by density, and the dummy comprehensive optimization method based on the CMP simulation model has obvious advantages.

Description

technical field

[0001] The invention belongs to the technology for copper interconnect dummy metal filling in the field of semiconductor manufacturability design, and in particular relates to a dummy comprehensive optimization method based on a CMP simulation model. Background technique

[0002] The development of the integrated circuit industry is an important driving force to promote the progress of social informatization. As the integrated circuit manufacturing process enters the nanometer scale, the increasingly serious process deviation seriously affects the performance and yield of the chip. Manufacturing deviations in processes such as chemical mechanical polishing (CMP: Chemical Mechanical Planarization) and photolithography clearly show the dependence on layout graphics (Pattern Dependent). The CMP process will produce dishing (Disshing) and erosion (Erosion) defects on the surface of the silicon wafer [1][2]. On the one hand, it will affect the focus and imaging ...

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