Dummy comprehensive optimization method based on CMP simulation model

A technology of simulation model and optimization method, applied in special data processing applications, instruments, electrical and digital data processing, etc., can solve the problem of too conservative filling constraints, unable to guarantee the final dummy effect, etc.

Active Publication Date: 2014-01-29
FUDAN UNIV
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  • Application Information

AI Technical Summary

Problems solved by technology

There is a "ditch" between the traditional density rule-driven dummy filling method and the ultimate goal, that is, the uniform distribution of parameters such as density and density gradient does not necessarily lead to the conclusion that the surface morphology of the chip after CMP polishing is smooth
This dumm

Method used

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  • Dummy comprehensive optimization method based on CMP simulation model
  • Dummy comprehensive optimization method based on CMP simulation model
  • Dummy comprehensive optimization method based on CMP simulation model

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Experimental program
Comparison scheme
Effect test

Embodiment 1

[0106] Embodiment 1 Comparison between the method of the present invention and the traditional rule-based dummy synthesis method on the CMP height topography results

[0107] The purpose of introducing CMP model simulation in the dummy filling process is to obtain a smoother chip surface after CMP polishing the filled layout. We use a full-chip CMP simulator to simulate the layout obtained by different dummy filling methods, calculate the mean square error of the chip surface height profile, and use this value to measure the filling quality of different dummy filling methods. The smaller the mean square error, the better the flatness of the chip surface, and the better the effect of dummy filling. The formula for calculating the mean square error is:

[0108] σ = 1 m × n Σ i = ...

Embodiment 2

[0111] Embodiment 2 The comparison between the method of the present invention and the traditional rule-based dummy synthesis method on CPU computing time

[0112] In this embodiment, different dummy filling methods are tested on problems of different scales. Figure 7 Execution times for 3 different filling methods are given. It can be seen from the figure that the linear programming method is the fastest to solve small-scale problems, but because its time complexity is O(n 3 ), the time increases rapidly. The two dummy filling methods based on the CMP model simulation need to call the CMP simulator repeatedly, and the time overhead is large, but the important thing is that they are not sensitive to the problem scale. The experimental data shows that the time complexity is about O(n), so In large-scale problems, it is much faster than the density-driven linear programming method.

[0113] Comparing the two model-based dummy filling methods, the FMF method is about 6 times ...

Embodiment 3

[0114] Embodiment 3 Comparison between the method of the present invention and the traditional rule-based dummy element synthesis method after filling the layout graphic features

[0115] In order to further analyze the difference in filling effect between the dummy filling method based on CMP model simulation and the dummy filling method driven by density rules, Table 1 counts the graphic features of the layout obtained by different dummy filling methods. In Table 1, three The number of dummy insertions of the two methods is basically the same.

[0116] Table 1 The density distribution characteristics of the results of different dummy filling methods

[0117]

[0118] As can be seen from Table 1, the minimum window density after filling (0.26) of the density rule-driven method is much higher than that of the two model-based dummy filling methods (0.187 and 0.193, respectively). In fact, this value is the lower bound of the window density. The density rule-driven method f...

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Abstract

The invention belongs to the field of manufacturability design of semiconductors and particularly relates to a dummy comprehensive optimization method based on a CMP simulation model for the copper-connection dummy metal filling technology. According to the method, the height morphology of the surface of a chip after undergoing CMP is obtained through full-chip CMP simulation, and an effective hot spot region with intense height changes is obtained; step-by-step dummy filling and fast CMP simulation of local regions are carried out iteratively in the effective hot spot region to gradually eliminate hot spots; finally, it is assured that no effective hot spot exists through the full-chip CMP simulation. Compared with a dummy comprehensive method based on rules, the dummy comprehensive optimization method based on the CMP simulation model can ensure that the height deviation of a layout after dummy filling and the CMP is within a given deviation threshold, and the dummy filling amount is small. Experiments show that in the same filling amount, the mean-square error ratio of the height morphology obtained respectively through the SMDF dummy filling method and the FMF dummy filling method is 58% smaller than that of the height morphology obtained through the dummy filling method driven by density, and the dummy comprehensive optimization method based on the CMP simulation model has obvious advantages.

Description

technical field [0001] The invention belongs to the technology for copper interconnect dummy metal filling in the field of semiconductor manufacturability design, and in particular relates to a dummy comprehensive optimization method based on a CMP simulation model. Background technique [0002] The development of the integrated circuit industry is an important driving force to promote the progress of social informatization. As the integrated circuit manufacturing process enters the nanometer scale, the increasingly serious process deviation seriously affects the performance and yield of the chip. Manufacturing deviations in processes such as chemical mechanical polishing (CMP: Chemical Mechanical Planarization) and photolithography clearly show the dependence on layout graphics (Pattern Dependent). The CMP process will produce dishing (Disshing) and erosion (Erosion) defects on the surface of the silicon wafer [1][2]. On the one hand, it will affect the focus and imaging ...

Claims

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Application Information

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IPC IPC(8): G06F17/50
Inventor 曾璇严昌浩陶俊周星宝武鹏
Owner FUDAN UNIV
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